专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US06505099B1 Radiant energy control system 失效
标题翻译：辐射能量控制系统
公开(公告)号：US06505099B1
公开(公告)日：2003-01-07
申请号：US09172783
申请日：1998-10-14
申请人： Martin S. Brice , Gordon M. Kay , Peter W. Cook
发明人： Martin S. Brice , Gordon M. Kay , Peter W. Cook
IPC分类号： G01M138
CPC分类号： F24D19/10 , F24D5/08 , G05D23/19
摘要： In a radiant energy heating system having one or more types of radiant energy heating sub-systems, a control system comprising a solid state electronic control panel pre-programmed to control two or more of the types of radiant heating sub-systems, wherein the control panel controls one or more of the types of sub-systems.
摘要翻译：在具有一种或多种类型的辐射能量加热子系统的辐射能量加热系统中，控制系统包括预编程以控制两种或多种辐射加热子系统的固态电子控制面板，其中控制面板控制一个或多个类型的子系统。

12. 发明授权

US5301340A IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to every register file per cycle 失效
标题翻译： IC芯片包括ALU和相同的寄存器文件，由此多个ALU直接并且同时向每个周期的每个寄存器文件写入结果
公开(公告)号：US5301340A
公开(公告)日：1994-04-05
申请号：US607176
申请日：1990-10-31
申请人： Peter W. Cook
发明人： Peter W. Cook
IPC分类号： G06F9/30 , G06F9/34 , G06F9/38 , G06F15/80 , G06F15/76
CPC分类号： G06F9/3891 , G06F15/8015 , G06F9/3012 , G06F9/3885 , G06F9/3887
摘要： A parallel computer architecture incorporates a new register file organization for parallel ALUs that provides improved performance due to reduced off-chip crossings and locally higher density. Each ALU is provided with its own, smaller register file located on the ALU chip. Data written by one ALU is "broadcast" to all the "local" register files. This arrangement of "local" register files minimizes the number of pins required and, using very large scale integration (VLSI) techniques, high densities can be achieved. These "local" register files eliminate off-chip delays, and performance is further enhanced by the shorter wire lengths in the local register files.
摘要翻译：并行计算机体系结构包含用于并行ALU的新的寄存器文件组织，由于减少的片外交叉和局部更高的密度，提供了改进的性能。每个ALU都配有自己的较小的寄存器文件，位于ALU芯片上。由一个ALU写入的数据被“广播”到所有的“本地”寄存器文件。这种“本地”寄存器文件的布置使所需的引脚数量最小化，并且使用非常大规模的集成（VLSI）技术可以实现高密度。这些“本地”寄存器文件消除了片外延迟，并且通过本地寄存器文件中较短的线长进一步增强了性能。

13. 发明授权

US4931971A Partial decode shifter/rotator 失效
标题翻译：部分解码移位器/旋转器
公开(公告)号：US4931971A
公开(公告)日：1990-06-05
申请号：US297170
申请日：1989-01-13
申请人： Peter W. Cook , Robert K. Montoye
发明人： Peter W. Cook , Robert K. Montoye
IPC分类号： G06F5/01 , G06F7/00 , G06F7/76
CPC分类号： G06F5/015
摘要： A data shifter/rotator which is comprised of two levels of s, where s is an integer >2, way switches. The outputs of the first level are connected to the corresponding inputs of the second level. There are first and second control words, with the first control word controlling the amount of the shift/rotation in the first level, and the second control word controlling the amount of the shift/rotation in the second level. The amount of the shift/rotation is determined by the position of the s way switches in each level, as selected by the respective control words.

14. 发明授权

US4931970A Apparatus for determining if there is a loss of data during a shift operation 失效
标题翻译：用于确定在换档操作期间是否有数据丢失的装置
公开(公告)号：US4931970A
公开(公告)日：1990-06-05
申请号：US297639
申请日：1989-01-13
申请人： Peter W. Cook , Robert K. Montoye
发明人： Peter W. Cook , Robert K. Montoye
IPC分类号： G06F7/00 , G06F5/01 , G06F7/76
CPC分类号： G06F5/015 , G06F7/49952
摘要： Apparatus for determining if, during the shifting of data there has been a loss of precision due to the loss of one or more data bits due to overflow. A small data field is shifted into a much larger data, field. The width of the switching mechanism used is based on the number of bits in the small data field. Loss of data is determined in part by ORing the control signals utilized to shift the small data field to the large data field.

15. 发明授权

US06952113B2 Method of reducing leakage current in sub one volt SOI circuits 有权
标题翻译：降低亚一伏SOI电路漏电流的方法
公开(公告)号：US06952113B2
公开(公告)日：2005-10-04
申请号：US10644211
申请日：2003-08-20
申请人： Richard B. Brown , Ching-Te K. Chuang , Peter W. Cook , Koushik K. Das , Rajiv V. Joshi
发明人： Richard B. Brown , Ching-Te K. Chuang , Peter W. Cook , Koushik K. Das , Rajiv V. Joshi
IPC分类号： H03K19/00 , A03K19/003
CPC分类号： H03K19/0016
摘要： A multi-threshold integrated circuit (IC) with reduced subthreshold leakage and method of reducing leakage. Selectable supply switching devices (NFETs and/or PFETs) between a logic circuit and supply connections (Vdd and Ground) for the circuit have higher thresholds than normal circuit devices. Some devices may have thresholds lowered when the supply switching devices are on. Header/footer devices with further higher threshold voltages and widths may be used to further increase off resistance and maintain/reduce on resistance. Alternatively, high threshold devices may be stacked to further reduce leakage to a point achieved for an even higher threshold. Intermediate supply connects at the devices may have decoupling capacitance and devices may be tapered for optimum stack height and an optimum taper ratio to minimize circuit leakage and circuit delay.
摘要翻译：具有降低的亚阈值泄漏的多阈值集成电路（IC）和减少泄漏的方法。电路逻辑电路和电源连接（V SUB）和GND之间的可选供电开关器件（NFET和/或PFET）的电路具有比正常电路器件更高的阈值。当供电开关装置打开时，一些装置可能具有降低的阈值。具有更高阈值电压和宽度的标题/页脚装置可用于进一步降低电阻和保持/降低电阻。或者，可以堆叠高阈值装置以进一步将泄漏减少到达到甚至更高阈值所达到的点。中间电源连接在器件上可能具有去耦电容，器件可以锥形化，以获得最佳堆叠高度和最佳锥度比，以最大限度地减少电路泄漏和电路延迟。

16. 发明授权

US06608771B2 Low-power circuit structures and methods for content addressable memories and random access memories 失效
标题翻译：用于内容可寻址存储器和随机存取存储器的低功率电路结构和方法
公开(公告)号：US06608771B2
公开(公告)日：2003-08-19
申请号：US09933189
申请日：2001-08-20
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Stanley Everett Schuster , Peter W. Cook
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Stanley Everett Schuster , Peter W. Cook
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A method is provided for associating an address with data. The method includes precharging a matchline connected to a plurality of tag match functions to a first potential, wherein each tag match function comprises one or more match logic devices, discharging two tag lines for a first tag bit to ground, and reading a plurality of tag bits and corresponding data bits onto a plurality of tag lines and a plurality of data lines respectively. The method further includes determining a match between the tag bits and data bits, and pulling the matchline to a second potential upon determining a match for each of the tag bits.
摘要翻译：提供了一种用于将地址与数据相关联的方法。该方法包括将连接到多个标签匹配功能的匹配线预先充电到第一电位，其中每个标签匹配功能包括一个或多个匹配逻辑器件，将用于第一标签位的两个标签行放电到地，以及读取多个标签位和相应的数据位分别分配到多个标签行和多条数据线上。该方法还包括确定标签位和数据位之间的匹配，并且在确定每个标签位的匹配时，将匹配线拉到第二电位。

17. 发明授权

US06512397B1 Circuit structures and methods for high-speed low-power select arbitration 失效
标题翻译：用于高速低功耗选择仲裁的电路结构和方法
公开(公告)号：US06512397B1
公开(公告)日：2003-01-28
申请号：US09933188
申请日：2001-08-20
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Peter W. Cook , Stanley Everett Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Peter W. Cook , Stanley Everett Schuster
IPC分类号： H03K1720
CPC分类号： G06F13/14 , Y02D10/14
摘要： A method is provided for selecting a participant to issue. The method includes signaling a domino OR gate arbitration device upon a ready request of a participant having a priority, determining within the domino OR gate arbitration device the relative priority of the participant, signaling the domino OR gate arbitration device through an any-request device upon the ready request of a higher priority participant, and issuing the higher priority participant upon determining the higher priority participant to have a priority highest among participants ready for issue. The method includes gating one of a precharge signal and an evaluate signal of the precharged domino OR gate arbitration device by the ready request of the participant. The method further includes latching a result of the domino OR gate arbitration device and a clock signal, and gating the clock signal by the ready signal of the participant.
摘要翻译：提供了一种用于选择参与者发行的方法。该方法包括在具有优先权的参与者的就绪请求之后发信号通知多米诺骨牌或门仲裁装置，在多米诺诺或门仲裁装置内确定参与者的相对优先级，通过任何请求装置向多米诺骨牌或门仲裁装置发信号确定较高优先权的参与者的准备好的请求，并且在确定较高优先权的参与者之后发出优先权较高的参与者以便在准备发行的参与者中具有最高优先权。该方法包括通过参与者的就绪请求选通预充电多米诺OR门仲裁装置的预充电信号和评估信号之一。该方法还包括锁存多米诺OROR仲裁装置的结果和时钟信号，并通过参与者的就绪信号门控时钟信号。

18. 发明授权

US5148059A CMOS and ECL logic circuit requiring no interface circuitry 失效
标题翻译： CMOS和ECL逻辑电路不需要接口电路
公开(公告)号：US5148059A
公开(公告)日：1992-09-15
申请号：US679363
申请日：1991-04-02
申请人： Chih-Liang Chen , Peter W. Cook , Lewis M. Terman
发明人： Chih-Liang Chen , Peter W. Cook , Lewis M. Terman
IPC分类号： H03K19/0175 , H03K19/08 , H03K19/086 , H03K19/0944
CPC分类号： H03K19/09448 , H03K19/017527 , H03K19/086
摘要： An ECL circuit (12) for directly coupling to and from a CMOS circuit (10). The ECL circuit has an input node for receiving an input signal generated by a CMOS circuit. The input signal swings, or transitions, between a first potential (V.sub.0) and a second potential (V.sub.1). The ECL circuit further includes ECL core circuitry (Q.sub.3, Q.sub.4, R.sub.L), coupled to the input node and responsive the received signal, for generating an intermediate electrical signal that swings between a third potential (V.sub.2) and a fourth potential (V.sub.3) that is approximately two times (V.sub.1 -V.sub.0). The ECL circuit further includes an output driver circuit for coupling to an input of a CMOS circuit or to another ECL circuit. The output driver circuit has an input node coupled to an output of the ECL core circuitry and includes emitter followers (EF.sub.1, EF.sub.2) for generating, in response to the intermediate electrical signal swinging between V.sub.2 and V.sub.3, a first output signal tha swings between the V.sub.0 and V.sub.1.
摘要翻译：用于直接耦合到CMOS电路（10）的ECL电路（12）。 ECL电路具有用于接收由CMOS电路产生的输入信号的输入节点。输入信号在第一电位（V0）和第二电位（V1）之间摆动或转变。 ECL电路还包括耦合到输入节点并响应于接收信号的ECL核心电路（Q3，Q4，RL），用于产生在第三电位（V2）和第四电位（V3）之间摆动的中间电信号，大约是两倍（V1-V0）。 ECL电路还包括用于耦合到CMOS电路的输入或另一ECL电路的输出驱动器电路。输出驱动器电路具有耦合到ECL核心电路的输出的输入节点，并且包括发射极跟随器（EF1，EF2），用于响应于V2和V3之间的中间电信号摆动而产生第一输出信号， V0和V1。

19. 发明授权

US4504924A Carry lookahead logical mechanism using affirmatively referenced transfer gates 失效
标题翻译：使用肯定引用的传输门进行前瞻逻辑机制
公开(公告)号：US4504924A
公开(公告)日：1985-03-12
申请号：US392828
申请日：1982-06-28
申请人： Peter W. Cook , Hung-Hui Hsieh , Glen S. Miranker
发明人： Peter W. Cook , Hung-Hui Hsieh , Glen S. Miranker
IPC分类号： H03K19/173 , G06F7/50 , G06F7/505 , G06F7/506 , G06F7/508
CPC分类号： G06F7/505
摘要： Complex logical mechanism, for simultaneously producing output signals related logically to a set of input signals, implemented in transfer gate pairs. The first transfer gate of each pair is connected generally in series and is controlled by conduction according to the signals applied. The second transfer gate of each pair shunts the output node of its related first transfer gate to ground, when enabled by a control signal complementary to the data pattern applied to the first transfer gate of the pair. This direct control of line voltages affirmatively drives the lines or affirmatively grounds the lines to eliminate back circuits.Carry propagation to higher order bit positions is along carry propagate lines, with series connected carry propagate first transfer gates. Order positions not having data values appropriate for carry propagation do not transmit carry values--these transfer gates are not controlled for conduction, but are nonetheless subject to possible back circuits. Carry propagate negation second transfer gates, connected in respective pairs with the carry propagate first transfer gates, are controlled by signals complementary to the control signals for the respectively carry propagate transfer gates, and, when enabled, connect the output nodes of the respective carry propagate first transfer gates directly to ground reference potential.
摘要翻译：复杂的逻辑机制，用于同时产生与传输门对实现的一组输入信号逻辑相关的输出信号。每对的第一传输门通常串联连接，并根据施加的信号通过导通来控制。当通过与施加到该对的第一传输门的数据模式互补的控制信号使能时，每对的第二传输门将其相关的第一传输门的输出节点分流到地。线路电压的这种直接控制肯定地驱动线路或肯定地使线路消除反向电路。携带传播到较高位位置沿着传播线，串联连接传播第一传输门。没有适合于进位传播的数据值的顺序位置不传送进位值 - 这些传送门不受控制用于传导，但仍然受到可能的反向电路的影响。携带传播第二传输门，与进位传播第一传输门分别成对连接，由与分别传送传输门的控制信号互补的信号控制，并且当使能时，连接各个传送传播的输出节点第一传输门直接到地参考电位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式