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11. 发明授权

US07384804B2 Method and apparatus for electronically aligning capacitively coupled mini-bars 有权
标题翻译：用于电容对齐电容耦合迷你条的方法和装置
公开(公告)号：US07384804B2
公开(公告)日：2008-06-10
申请号：US11125792
申请日：2005-05-09
申请人： Robert J. Drost , Ivan E. Sutherland , William S. Coates
发明人： Robert J. Drost , Ivan E. Sutherland , William S. Coates
IPC分类号： H01L21/66
CPC分类号： H01L25/0657 , H01L23/48 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/00011 , H01L2924/00014 , H01L2924/01067 , H01L2224/0401
摘要： One embodiment of the present invention provides a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system measures an alignment between a first chip and a second chip. The system then selects a group of transmitter mini-bars on the first chip to form a transmitter bit position based on the measured alignment. In this way, the system allows a data signal to be distributed to and transmitted by the mini-bars that form the transmitter bit position. The system also selects a group of receiver mini-bars on the second chip to form a receiver bit position based on the measured alignment. Next, the system associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip based on the measured alignment. In this way, the system allows data signals transmitted by the mini-bars within a transmitter bit position on the first chip to be collectively received by the mini-bars within an associated receiver bit position on the second chip.
摘要翻译：本发明的一个实施例提供了一种系统，其电子地对准位于面对面的不同半导体芯片上的迷你条，以促进半导体芯片之间通过电容耦合的通信。在操作期间，系统测量第一芯片和第二芯片之间的对准。然后，系统在第一芯片上选择一组发射器迷你条，以基于测量的对准来形成发射机位置。以这种方式，该系统允许将数据信号分配到形成发送器位位置的迷你条并发送。该系统还在第二芯片上选择一组接收器迷你条，以形成基于测量对准的接收器位位置。接下来，系统基于测量的对准将第一芯片上的发射机位位置与第二芯片上的接收器位置相关联。以这种方式，系统允许由第一芯片上的发送器位置内的迷你条发送的数据信号由第二芯片上相关联的接收器位位置内的迷你条集中接收。

12. 发明授权

US06987412B2 Sense amplifying latch with low swing feedback 有权
标题翻译：具有低摆动反馈的感应放大锁存器
公开(公告)号：US06987412B2
公开(公告)日：2006-01-17
申请号：US10816761
申请日：2004-04-02
申请人： Ivan E. Sutherland , Robert J. Bosnyak , Robert J. Drost
发明人： Ivan E. Sutherland , Robert J. Bosnyak , Robert J. Drost
IPC分类号： H03K3/356 , H03L5/00
CPC分类号： H03K5/003 , H01L23/48 , H01L25/0657 , H01L2225/06527 , H01L2924/00013 , H01L2924/0002 , H03K3/037 , H03K17/689 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： A system is presented for latching and amplifying a capacitively coupled inter-chip communication signal that operates by receiving an input signal on a capacitive receiver pad and feeding the input signal through an inverter to produce an output signal. The output signal is fed back through a weakened inverter to produce a feedback signal that is fed into an input of the inverter to form a latch for the input signal. The weakened inverter is biased to produce a feedback signal that swings between a high bias voltage, VH, and a low bias voltage, VL. VH is set slightly higher than the switching threshold of the inverter, and VL is set slightly lower than the switching threshold. This feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal.
摘要翻译：提出了一种用于锁存和放大电容耦合的芯片间通信信号的系统，其通过接收电容性接收器焊盘上的输入信号并通过反相器馈送输入信号以产生输出信号来操作。输出信号通过弱化逆变器反馈，产生反馈信号，该反馈信号馈送到反相器的输入端，形成输入信号的锁存器。弱化的逆变器被偏置以产生在高偏置电压V H H和低偏压V L之间摆动的反馈信号。 V H设定得比逆变器的切换阈值略高，并且将V L L设定得比切换阈值略低。该反馈信号使得输入信号驻留在接近逆变器的开关阈值的窄电压范围内，从而使得反相器对输入信号中的小转变敏感。

13. 发明授权

US06825708B1 Apparatus and method for an offset-correcting sense amplifier 有权
标题翻译：偏移校正读出放大器的装置和方法
公开(公告)号：US06825708B1
公开(公告)日：2004-11-30
申请号：US10697914
申请日：2003-10-29
申请人： Robert J. Drost , Ivan E. Sutherland
发明人： Robert J. Drost , Ivan E. Sutherland
IPC分类号： G06G712
CPC分类号： H03K5/003 , H01L23/48 , H01L25/0657 , H01L2225/06527 , H01L2924/0002 , H01L2924/3011 , H03F1/301 , H03F1/342 , H01L2924/00
摘要： An apparatus and method for a sensing circuit for cancelling an offset voltage. Specifically, in one embodiment, a CMOS inverter amplifier amplifies an input signal present at an input node. A resistive feedback circuit is coupled to the CMOS inverter amplifier for cancelling an offset voltage that is associated with the CMOS inverter amplifier. This is accomplished by biasing the CMOS inverter amplifier to its threshold voltage. A bias circuit is coupled to the resistive feedback circuit for biasing MOSFET transistors in the resistive feedback circuit at a subthreshold conduction region. As such, the resistive feedback circuit presents a high impedance to the input node. A clamping circuit, coupled to the resistive feedback circuit, maintains operation of the transistors in the resistive feedback circuit in the subthreshold conduction region.
摘要翻译：一种用于消除偏移电压的感测电路的装置和方法。具体地，在一个实施例中，CMOS反相放大器放大存在于输入节点处的输入信号。电阻反馈电路耦合到CMOS反相放大器，用于消除与CMOS反相放大器相关联的偏移电压。这通过将CMOS反相放大器偏置到其阈值电压来实现。偏置电路耦合到电阻反馈电路，用于在亚阈值导通区域偏置电阻反馈电路中的MOSFET晶体管。因此，电阻反馈电路对输入节点呈现高阻抗。耦合到电阻反馈电路的钳位电路在亚阈值导通区域中保持电阻反馈电路中的晶体管的操作。

14. 发明授权

US07994501B2 Method and apparatus for electronically aligning capacitively coupled mini-bars 有权
标题翻译：用于电容对齐电容耦合迷你条的方法和装置
公开(公告)号：US07994501B2
公开(公告)日：2011-08-09
申请号：US12114404
申请日：2008-05-02
申请人： Robert J. Drost , Ivan E. Sutherland , William S. Coates
发明人： Robert J. Drost , Ivan E. Sutherland , William S. Coates
IPC分类号： H01L23/58 , H01L29/10
CPC分类号： H01L25/0657 , H01L23/48 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/00011 , H01L2924/00014 , H01L2924/01067 , H01L2224/0401
摘要： Embodiments of the present invention provide a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system selects a group of transmitter mini-bars on the first chip to form a transmitter bit position and selects a group of receiver mini-bars on the second chip to form a receiver bit position. The system then associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip. In this way, the system allows data signals transmitted by the mini-bars within a transmitter bit position on the first chip to be collectively received by the mini-bars within an associated receiver bit position on the second chip.
摘要翻译：本发明的实施例提供了一种系统，其将面对面地定位在不同半导体芯片上的迷你条电子对准以便于通过电容耦合来促进半导体芯片之间的通信。在操作期间，系统在第一芯片上选择一组发射机迷你条来形成发射机位位置，并在第二芯片上选择一组接收器迷你条来形成接收器位位置。然后，系统将第一芯片上的发送器位置与第二芯片上的接收器位置相关联。以这种方式，系统允许由第一芯片上的发送器位置内的迷你条发送的数据信号由第二芯片上相关联的接收器位位置内的迷你条集中接收。

15. 发明授权

US06870271B2 Integrated circuit assembly module that supports capacitive communication between semiconductor dies 有权
标题翻译：集成电路组件模块，支持半导体管芯之间的电容连接
公开(公告)号：US06870271B2
公开(公告)日：2005-03-22
申请号：US10671642
申请日：2003-09-26
申请人： Ivan E. Sutherland , Robert J. Drost , Gary R. Lauterbach , Howard L. Davidson
发明人： Ivan E. Sutherland , Robert J. Drost , Gary R. Lauterbach , Howard L. Davidson
IPC分类号： H01L25/18 , H01L23/367 , H01L23/473 , H01L23/48 , H01L25/04 , H01L25/065 , H01L23/52 , H05K7/00
CPC分类号： H01L23/48 , H01L23/367 , H01L23/473 , H01L25/0652 , H01L2225/06513 , H01L2225/06534 , H01L2225/06589 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention provides an integrated circuit assembly module, including a first semiconductor die and a second semiconductor die, each semiconductor die with an active face upon which active circuitry and signal pads reside and a back face opposite the active face. The first and second semiconductor dies are positioned face-to-face within the assembly module so that signal pads on the first semiconductor die overlap with signal pads on the second semiconductor die, thereby facilitating capacitive communication between the first and second semiconductor dies. Additionally, the first and second semiconductor dies are pressed together between a first substrate and a second substrate so that a front side of the first substrate is in contact with the back face of the first semiconductor die and a front side of the second substrate is in contact with the back face of the second semiconductor die.
摘要翻译：本发明的一个实施例提供了一种集成电路组件模块，其包括第一半导体管芯和第二半导体管芯，每个具有有源面的半导体管芯具有有源电路和信号焊盘的位置以及与该有源面相对的背面。第一和第二半导体管芯在组件模块内面对面地定位，使得第一半导体管芯上的信号焊盘与第二半导体管芯上的信号焊盘重叠，从而有助于第一和第二半导体管芯之间的电容连通。此外，第一和第二半导体管芯在第一基板和第二基板之间被压在一起，使得第一基板的前侧与第一半导体管芯的背面接触，并且第二基板的前侧处于与第二半导体管芯的背面接触。

16. 发明申请

US20080208521A1 METHOD AND APPARATUS FOR ELECTRONICALLY ALIGNING CAPACITIVELY COUPLED MNI-BARS 有权
标题翻译：电子联结电容式MNI-BARS的方法与装置
公开(公告)号：US20080208521A1
公开(公告)日：2008-08-28
申请号：US12114404
申请日：2008-05-02
申请人： Robert J. Drost , Ivan E. Sutherland , William S. Coates
发明人： Robert J. Drost , Ivan E. Sutherland , William S. Coates
IPC分类号： G01C9/00
CPC分类号： H01L25/0657 , H01L23/48 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/00011 , H01L2924/00014 , H01L2924/01067 , H01L2224/0401
摘要： Embodiments of the present invention provide a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system selects a group of transmitter mini-bars on the first chip to form a transmitter bit position and selects a group of receiver mini-bars on the second chip to form a receiver bit position. The system then associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip. In this way, the system allows data signals transmitted by the mini-bars within a transmitter bit position on the first chip to be collectively received by the mini-bars within an associated receiver bit position on the second chip.
摘要翻译：本发明的实施例提供了一种系统，其将面对面地定位在不同半导体芯片上的迷你条电子对准以便于通过电容耦合来促进半导体芯片之间的通信。在操作期间，系统在第一芯片上选择一组发射机迷你条来形成发射机位位置，并在第二芯片上选择一组接收器迷你条来形成接收器位位置。然后，系统将第一芯片上的发送器位置与第二芯片上的接收器位置相关联。以这种方式，系统允许由第一芯片上的发送器位置内的迷你条发送的数据信号由第二芯片上相关联的接收器位位置内的迷你条集中接收。

17. 发明授权

US07417993B1 Apparatus and method for high-throughput asynchronous communication 有权
标题翻译：高吞吐量异步通信的装置和方法
公开(公告)号：US07417993B1
公开(公告)日：2008-08-26
申请号：US10742075
申请日：2003-12-18
申请人： Josephus C. Ebergen , Ivan E. Sutherland , Robert J. Drost
发明人： Josephus C. Ebergen , Ivan E. Sutherland , Robert J. Drost
IPC分类号： H04L12/28 , H04L12/56 , H04L1/00
CPC分类号： H04L49/901 , H04L49/90
摘要： One embodiment of the present invention provides a system for high-throughput asynchronous communication that includes a sender and a receiver. A sender's first-in, first-out (FIFO) buffer is coupled to an input of the sender, a receiver's FIFO buffer is coupled to an input of the receiver, a forward communication channel is coupled between the sender and the receiver's FIFO buffer, and a reverse communication channel is coupled between the receiver and the sender's FIFO buffer. The forward communication channel, the receiver's FIFO buffer, the reverse communication channel, and the sender's FIFO buffer operate collectively as a network FIFO between the sender and the receiver. The network FIFO is configured to ensure that asynchronous communication between the sender and the receiver takes place reliably and without unnecessary waiting by the sender or the receiver.
摘要翻译：本发明的一个实施例提供一种包括发送器和接收器的用于高吞吐量异步通信的系统。发送方的先进先出（FIFO）缓冲器耦合到发送方的输入，接收器的FIFO缓冲器耦合到接收器的输入，前向通信信道耦合在发送方和接收方的FIFO缓冲器之间，并且反向通信信道耦合在接收器和发送器的FIFO缓冲器之间。前向通信信道，接收机的FIFO缓冲区，反向通信信道和发送方的FIFO缓冲区共同作为发送方和接收方之间的网络FIFO进行操作。网络FIFO被配置为确保发送器和接收器之间的异步通信可靠地发生，并且不需要由发送器或接收器等待。

18. 发明授权

US06995039B2 Method and apparatus for electrostatically aligning integrated circuits 有权
标题翻译：集成电路静电对准的方法和装置
公开(公告)号：US06995039B2
公开(公告)日：2006-02-07
申请号：US10759923
申请日：2004-01-15
申请人： David L. Harris , Robert J. Drost , Ivan E. Sutherland
发明人： David L. Harris , Robert J. Drost , Ivan E. Sutherland
IPC分类号： H01L21/44
CPC分类号： H01L24/95 , H01L23/50 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2223/6622 , H01L2224/13012 , H01L2224/81121 , H01L2224/81801 , H01L2224/95145 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01039 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/0401
摘要： One embodiment of the present invention provides a system that uses electrostatic forces to align semiconductor chips relative to each other. The system operates by fabricating a first set of conductors on the top surface of a first chip and fabricating a corresponding second set of conductors on the top surface of a second chip. To align the chips, the system electrically charges the first set of conductors and the second set of conductors. The system also places the first chip face-to-face with the second chip, so that the first set of conductors is in close proximity to the second set of conductors. This allows electrostatic forces between the first set of conductors and the second set of conductors to bring the first chip into alignment with the second chip and to hold them in place.
摘要翻译：本发明的一个实施例提供一种使用静电力使半导体芯片相对于彼此对准的系统。该系统通过在第一芯片的顶表面上制造第一组导体并在第二芯片的顶表面上制造相应的第二组导体来操作。为了对准芯片，系统对第一组导体和第二组导体进行电荷充电。该系统还将第一芯片与第二芯片面对面地放置，使得第一组导体紧邻第二组导体。这允许第一组导体和第二组导体之间的静电力使第一芯片与第二芯片对准并将其保持就位。

19. 发明授权

US06925411B1 Method and apparatus for aligning semiconductor chips using an actively driven vernier 有权
标题翻译：使用主动驱动游标对准半导体芯片的方法和装置
公开(公告)号：US06925411B1
公开(公告)日：2005-08-02
申请号：US10741961
申请日：2003-12-19
申请人： Robert J. Drost , Ivan E. Sutherland
发明人： Robert J. Drost , Ivan E. Sutherland
IPC分类号： G01C17/00 , H01L23/544
CPC分类号： H01L22/34 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06527 , H01L2225/06593 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： One embodiment of the present invention provides a system that facilitates measuring an alignment between a first semiconductor die and a second semiconductor die. The system provides a plurality of conductive elements on the first semiconductor die and a plurality of conductive elements on the second semiconductor die. The plurality of conductive elements on the second semiconductor die have a different spacing than the plurality of conductive elements on the first semiconductor die, so that when the plurality of conductive elements on the first semiconductor die overlap the plurality of conductive elements on the second semiconductor die, a vernier alignment structure is created between them. The system also provides a charging mechanism configured to selectively charge each of the plurality of conductive elements on the first semiconductor die, wherein charging a conductive element on the first semiconductor die induces a charge in one or more conductive elements on the second semiconductor die. An amplification mechanism then amplifies the signals induced in the conductive elements on the second semiconductor die. These signals can be analyzed to determine the alignment between the first semiconductor die and the second semiconductor die.
摘要翻译：本发明的一个实施例提供一种便于测量第一半导体管芯和第二半导体管芯之间的对准的系统。该系统在第一半导体管芯上提供多个导电元件，并在第二半导体管芯上提供多个导电元件。第二半导体管芯上的多个导电元件具有与第一半导体管芯上的多个导电元件不同的间隔，使得当第一半导体管芯上的多个导电元件与第二半导体管芯上的多个导电元件重叠时在它们之间创建游标对齐结构。该系统还提供了一种配置成选择性地对第一半导体管芯上的多个导电元件充电的充电机构，其中对第一半导体管芯上的导电元件充电在第二半导体管芯上的一个或多个导电元件中引起电荷。然后，放大机构放大在第二半导体管芯上的导电元件中感应的信号。可以分析这些信号以确定第一半导体管芯和第二半导体管芯之间的对准。

20. 发明授权

US06812046B2 Method and apparatus for electronically aligning capacitively coupled chip pads 有权
标题翻译：用于电子对准电容耦合芯片焊盘的方法和装置
公开(公告)号：US06812046B2
公开(公告)日：2004-11-02
申请号：US10207671
申请日：2002-07-29
申请人： Robert J. Drost , Ivan E. Sutherland , Gregory M. Papadopoulos
发明人： Robert J. Drost , Ivan E. Sutherland , Gregory M. Papadopoulos
IPC分类号： H01L2166
CPC分类号： H04B5/0012 , G06F17/5077 , H01L23/48 , H01L23/544 , H01L2223/54473 , H01L2225/06531 , H01L2924/0002 , H01L2924/0001
摘要： One embodiment of the present invention provides a system that electronically aligns pads on different semiconductor chips to facilitate communication between the semiconductor chips through capacitive coupling. The system operates by measuring an alignment between a first chip and a second chip, wherein the first chip is situated face-to-face with the second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip. Next, the system uses the measured alignment to associate transmitter pads on the first chip with proximate receiver pads on the second chip. The system then selectively routes data signals to transmitter pads on the first chip so that the data signals are communicated through capacitive coupling to intended receiver pads in the second chip that are proximate to the transmitter pads.
摘要翻译：本发明的一个实施例提供一种系统，其电子地对准不同半导体芯片上的焊盘，以便于通过电容耦合在半导体芯片之间进行通信。该系统通过测量第一芯片和第二芯片之间的对准来工作，其中第一芯片与第二芯片面对面设置，使得第一芯片上的发射器焊盘与第二芯片上的接收器焊盘电容耦合。接下来，系统使用测量的对准来将第一芯片上的发射器焊盘与第二芯片上的接近焊盘相关联。然后，系统选择性地将数据信号路由到第一芯片上的发射机焊盘，使得数据信号通过电容耦合传递到靠近发射器焊盘的第二芯片中的预期接收器焊盘。

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