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1. 发明授权

US07417993B1 Apparatus and method for high-throughput asynchronous communication 有权
标题翻译：高吞吐量异步通信的装置和方法
公开(公告)号：US07417993B1
公开(公告)日：2008-08-26
申请号：US10742075
申请日：2003-12-18
申请人： Josephus C. Ebergen , Ivan E. Sutherland , Robert J. Drost
发明人： Josephus C. Ebergen , Ivan E. Sutherland , Robert J. Drost
IPC分类号： H04L12/28 , H04L12/56 , H04L1/00
CPC分类号： H04L49/901 , H04L49/90
摘要： One embodiment of the present invention provides a system for high-throughput asynchronous communication that includes a sender and a receiver. A sender's first-in, first-out (FIFO) buffer is coupled to an input of the sender, a receiver's FIFO buffer is coupled to an input of the receiver, a forward communication channel is coupled between the sender and the receiver's FIFO buffer, and a reverse communication channel is coupled between the receiver and the sender's FIFO buffer. The forward communication channel, the receiver's FIFO buffer, the reverse communication channel, and the sender's FIFO buffer operate collectively as a network FIFO between the sender and the receiver. The network FIFO is configured to ensure that asynchronous communication between the sender and the receiver takes place reliably and without unnecessary waiting by the sender or the receiver.
摘要翻译：本发明的一个实施例提供一种包括发送器和接收器的用于高吞吐量异步通信的系统。发送方的先进先出（FIFO）缓冲器耦合到发送方的输入，接收器的FIFO缓冲器耦合到接收器的输入，前向通信信道耦合在发送方和接收方的FIFO缓冲器之间，并且反向通信信道耦合在接收器和发送器的FIFO缓冲器之间。前向通信信道，接收机的FIFO缓冲区，反向通信信道和发送方的FIFO缓冲区共同作为发送方和接收方之间的网络FIFO进行操作。网络FIFO被配置为确保发送器和接收器之间的异步通信可靠地发生，并且不需要由发送器或接收器等待。

2. 发明授权

US08222924B2 Asynchronous FIFO circuit for long-distance on-chip communication 有权
标题翻译：用于长距离片上通信的异步FIFO电路
公开(公告)号：US08222924B2
公开(公告)日：2012-07-17
申请号：US12954474
申请日：2010-11-24
申请人： William S. Coates , Robert J. Drost , Josephus C. Ebergen
发明人： William S. Coates , Robert J. Drost , Josephus C. Ebergen
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H04B3/36
摘要： The disclosed embodiments provide a first-in, first-out (FIFO) circuit that operates asynchronously. The FIFO circuit includes a data path that contains data latches sequentially connected through data-wire segments. The FIFO circuit also includes a control circuit that generates control signals for the data latches so that the data path behaves like a FIFO. The control circuit includes control components sequentially connected to each other through control-wire segments and repeaters located within the control-wire segments. The control components are configured to asynchronously generate the control signals for the data latches, and the repeaters are configured to repeat asynchronous signals communicated between the asynchronous control components.
摘要翻译：所公开的实施例提供异步操作的先入先出（FIFO）电路。 FIFO电路包括包含通过数据线段顺序连接的数据锁存器的数据路径。 FIFO电路还包括一个控制电路，该控制电路为数据锁存器产生控制信号，使得数据通路的行为类似于FIFO。控制电路包括通过控制线段和位于控制线段内的中继器而相互连接的控制组件。控制组件被配置为异步地生成用于数据锁存器的控制信号，并且中继器被配置为重复异步控制组件之间传送的异步信号。

3. 发明授权

US07256628B2 Speed-matching control method and circuit 有权
标题翻译：速度匹配控制方法和电路
公开(公告)号：US07256628B2
公开(公告)日：2007-08-14
申请号：US10671641
申请日：2003-09-26
申请人： Robert J. Drost , William S. Coates , Josephus C. Ebergen
发明人： Robert J. Drost , William S. Coates , Josephus C. Ebergen
IPC分类号： H03L7/06
CPC分类号： G06F1/12
摘要： One embodiment of the present invention provides a system that matches speeds of asynchronous operation between a local chip and a neighboring chip. The system derives an internal frequency signal from an internal oscillator on the local chip, and receives an external frequency signal from a neighboring chip. The system then compares the internal frequency signal with the external frequency signal to generate a control signal, which is applied to the local chip to adjust the operating speed of the local chip, and applied to the internal oscillator to adjust the frequency of the internal oscillator.
摘要翻译：本发明的一个实施例提供了一种匹配本地芯片和相邻芯片之间的异步操作速度的系统。该系统从本地芯片上的内部振荡器得到内部频率信号，并从相邻芯片接收外部频率信号。然后系统将内部频率信号与外部频率信号进行比较，以产生一个控制信号，该控制信号被施加到本地芯片上以调整本地芯片的工作速度，并施加到内部振荡器以调整内部振荡器的频率。

4. 发明申请

US20120128037A1 ASYNCHRONOUS FIFO CIRCUIT FOR LONG-DISTANCE ON-CHIP COMMUNICATION 有权
标题翻译：用于长距离片上通信的异步FIFO电路
公开(公告)号：US20120128037A1
公开(公告)日：2012-05-24
申请号：US12954474
申请日：2010-11-24
申请人： William S. Coates , Robert J. Drost , Josephus C. Ebergen
发明人： William S. Coates , Robert J. Drost , Josephus C. Ebergen
IPC分类号： H04B3/36 , G06F3/00
CPC分类号： H04B3/36
摘要： The disclosed embodiments provide a first-in, first-out (FIFO) circuit that operates asynchronously. The FIFO circuit includes a data path that contains data latches sequentially connected through data-wire segments. The FIFO circuit also includes a control circuit that generates control signals for the data latches so that the data path behaves like a FIFO. The control circuit includes control components sequentially connected to each other through control-wire segments and repeaters located within the control-wire segments. The control components are configured to asynchronously generate the control signals for the data latches, and the repeaters are configured to repeat asynchronous signals communicated between the asynchronous control components.
摘要翻译：所公开的实施例提供异步操作的先入先出（FIFO）电路。 FIFO电路包括包含通过数据线段顺序连接的数据锁存器的数据路径。 FIFO电路还包括一个控制电路，该控制电路为数据锁存器产生控制信号，使得数据通路的行为类似于FIFO。控制电路包括通过控制线段和位于控制线段内的中继器而相互连接的控制组件。控制组件被配置为异步地生成用于数据锁存器的控制信号，并且中继器被配置为重复异步控制组件之间传送的异步信号。

5. 发明授权

US07384804B2 Method and apparatus for electronically aligning capacitively coupled mini-bars 有权
标题翻译：用于电容对齐电容耦合迷你条的方法和装置
公开(公告)号：US07384804B2
公开(公告)日：2008-06-10
申请号：US11125792
申请日：2005-05-09
申请人： Robert J. Drost , Ivan E. Sutherland , William S. Coates
发明人： Robert J. Drost , Ivan E. Sutherland , William S. Coates
IPC分类号： H01L21/66
CPC分类号： H01L25/0657 , H01L23/48 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/00011 , H01L2924/00014 , H01L2924/01067 , H01L2224/0401
摘要： One embodiment of the present invention provides a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system measures an alignment between a first chip and a second chip. The system then selects a group of transmitter mini-bars on the first chip to form a transmitter bit position based on the measured alignment. In this way, the system allows a data signal to be distributed to and transmitted by the mini-bars that form the transmitter bit position. The system also selects a group of receiver mini-bars on the second chip to form a receiver bit position based on the measured alignment. Next, the system associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip based on the measured alignment. In this way, the system allows data signals transmitted by the mini-bars within a transmitter bit position on the first chip to be collectively received by the mini-bars within an associated receiver bit position on the second chip.
摘要翻译：本发明的一个实施例提供了一种系统，其电子地对准位于面对面的不同半导体芯片上的迷你条，以促进半导体芯片之间通过电容耦合的通信。在操作期间，系统测量第一芯片和第二芯片之间的对准。然后，系统在第一芯片上选择一组发射器迷你条，以基于测量的对准来形成发射机位置。以这种方式，该系统允许将数据信号分配到形成发送器位位置的迷你条并发送。该系统还在第二芯片上选择一组接收器迷你条，以形成基于测量对准的接收器位位置。接下来，系统基于测量的对准将第一芯片上的发射机位位置与第二芯片上的接收器位置相关联。以这种方式，系统允许由第一芯片上的发送器位置内的迷你条发送的数据信号由第二芯片上相关联的接收器位位置内的迷你条集中接收。

6. 发明授权

US07026867B2 Floating input amplifier for capacitively coupled communication 有权
标题翻译：用于电容耦合通信的浮动输入放大器
公开(公告)号：US07026867B2
公开(公告)日：2006-04-11
申请号：US10879606
申请日：2004-06-28
申请人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
发明人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
IPC分类号： H03F1/02
CPC分类号： H03F3/45977 , H03F3/08
摘要： One embodiment of the present invention provides a capacitively-coupled receiver amplifier that has an input with no DC coupling. A DC voltage is programmed on the input. During programming, a transmitter is held at a voltage at a midpoint between a voltage that represents a logical “1” and a voltage that represents a logical “0” and the input voltage of the receiver amplifier is programmed to be substantially the switching-threshold voltage for the receiver amplifier. Then, during normal data communication, the transmitter drives high and low electrical signals that are coupled to the receiver amplifier. Since the input of the receiver amplifier has been substantially set to the DC voltage, the receiver amplifier need not control the DC voltage of the input for each transition in the electrical signals.
摘要翻译：本发明的一个实施例提供一种具有不具有直流耦合的输入的电容耦合接收放大器。在输入端编程一个直流电压。在编程期间，发射机被保持在表示逻辑“1”的电压和表示逻辑“0”的电压之间的中点处的电压，并且接收机放大器的输入电压被编程为基本上是切换阈值接收放大器的电压。然后，在正常数据通信期间，发射机驱动耦合到接收放大器的高电平和低电信号。由于接收机放大器的输入已基本设置为直流电压，所以接收放大器不需要控制电信号中每个转换的输入的直流电压。

7. 发明授权

US06987412B2 Sense amplifying latch with low swing feedback 有权
标题翻译：具有低摆动反馈的感应放大锁存器
公开(公告)号：US06987412B2
公开(公告)日：2006-01-17
申请号：US10816761
申请日：2004-04-02
申请人： Ivan E. Sutherland , Robert J. Bosnyak , Robert J. Drost
发明人： Ivan E. Sutherland , Robert J. Bosnyak , Robert J. Drost
IPC分类号： H03K3/356 , H03L5/00
CPC分类号： H03K5/003 , H01L23/48 , H01L25/0657 , H01L2225/06527 , H01L2924/00013 , H01L2924/0002 , H03K3/037 , H03K17/689 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： A system is presented for latching and amplifying a capacitively coupled inter-chip communication signal that operates by receiving an input signal on a capacitive receiver pad and feeding the input signal through an inverter to produce an output signal. The output signal is fed back through a weakened inverter to produce a feedback signal that is fed into an input of the inverter to form a latch for the input signal. The weakened inverter is biased to produce a feedback signal that swings between a high bias voltage, VH, and a low bias voltage, VL. VH is set slightly higher than the switching threshold of the inverter, and VL is set slightly lower than the switching threshold. This feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal.
摘要翻译：提出了一种用于锁存和放大电容耦合的芯片间通信信号的系统，其通过接收电容性接收器焊盘上的输入信号并通过反相器馈送输入信号以产生输出信号来操作。输出信号通过弱化逆变器反馈，产生反馈信号，该反馈信号馈送到反相器的输入端，形成输入信号的锁存器。弱化的逆变器被偏置以产生在高偏置电压V H H和低偏压V L之间摆动的反馈信号。 V H设定得比逆变器的切换阈值略高，并且将V L L设定得比切换阈值略低。该反馈信号使得输入信号驻留在接近逆变器的开关阈值的窄电压范围内，从而使得反相器对输入信号中的小转变敏感。

8. 发明授权

US06825708B1 Apparatus and method for an offset-correcting sense amplifier 有权
标题翻译：偏移校正读出放大器的装置和方法
公开(公告)号：US06825708B1
公开(公告)日：2004-11-30
申请号：US10697914
申请日：2003-10-29
申请人： Robert J. Drost , Ivan E. Sutherland
发明人： Robert J. Drost , Ivan E. Sutherland
IPC分类号： G06G712
CPC分类号： H03K5/003 , H01L23/48 , H01L25/0657 , H01L2225/06527 , H01L2924/0002 , H01L2924/3011 , H03F1/301 , H03F1/342 , H01L2924/00
摘要： An apparatus and method for a sensing circuit for cancelling an offset voltage. Specifically, in one embodiment, a CMOS inverter amplifier amplifies an input signal present at an input node. A resistive feedback circuit is coupled to the CMOS inverter amplifier for cancelling an offset voltage that is associated with the CMOS inverter amplifier. This is accomplished by biasing the CMOS inverter amplifier to its threshold voltage. A bias circuit is coupled to the resistive feedback circuit for biasing MOSFET transistors in the resistive feedback circuit at a subthreshold conduction region. As such, the resistive feedback circuit presents a high impedance to the input node. A clamping circuit, coupled to the resistive feedback circuit, maintains operation of the transistors in the resistive feedback circuit in the subthreshold conduction region.
摘要翻译：一种用于消除偏移电压的感测电路的装置和方法。具体地，在一个实施例中，CMOS反相放大器放大存在于输入节点处的输入信号。电阻反馈电路耦合到CMOS反相放大器，用于消除与CMOS反相放大器相关联的偏移电压。这通过将CMOS反相放大器偏置到其阈值电压来实现。偏置电路耦合到电阻反馈电路，用于在亚阈值导通区域偏置电阻反馈电路中的MOSFET晶体管。因此，电阻反馈电路对输入节点呈现高阻抗。耦合到电阻反馈电路的钳位电路在亚阈值导通区域中保持电阻反馈电路中的晶体管的操作。

9. 发明授权

US07200830B2 Enhanced electrically-aligned proximity communication 有权
标题翻译：增强的电对齐邻近通信
公开(公告)号：US07200830B2
公开(公告)日：2007-04-03
申请号：US10879607
申请日：2004-06-28
申请人： Robert J. Drost , Ivan E. Sutherland , Ronald Ho
发明人： Robert J. Drost , Ivan E. Sutherland , Ronald Ho
IPC分类号： G06F17/50
CPC分类号： H01L23/48 , H01L25/0657 , H01L2225/06531 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention provides a system that facilitates capacitive inter-chip communication. During operation, the system first determines an alignment between a first semiconductor die and a second semiconductor die. Next, electrical signals are selectively routed to at least one interconnect pad in a plurality of interconnect pads based on the alignment thereby facilitating communication between the first semiconductor die and the second semiconductor die. The plurality of interconnect pads can include transmitting pads, receiving pads, and transmitting and receiving pads. The alignment may be determined continuously or at times separated by an interval, where the interval is fixed or variable. Several variations on this embodiment are provided.
摘要翻译：本发明的一个实施例提供一种便于电容芯片间通信的系统。在操作期间，系统首先确定第一半导体管芯和第二半导体管芯之间的对准。接下来，基于对准，电信号被选择性地路由到多个互连焊盘中的至少一个互连焊盘，从而便于第一半导体管芯和第二半导体管芯之间的连通。多个互连焊盘可以包括传输焊盘，接收焊盘以及发射和接收焊盘。可以连续地或有时间隔地间隔地确定对准，其中间隔是固定的或可变的。提供了该实施例的几个变型。

10. 发明授权

US07046017B1 Full-wave rectifier for capacitance measurements 有权
标题翻译：全波整流电容测量
公开(公告)号：US07046017B1
公开(公告)日：2006-05-16
申请号：US11216754
申请日：2005-08-30
申请人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
发明人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
IPC分类号： G01R27/26 , G01N27/22
CPC分类号： G01R27/2605
摘要： One embodiment of the present invention provides an electronic circuit and method for measuring a capacitance. A signal generating mechanism generates a signal having a predefined frequency and predefined low and high voltage levels on one terminal of the capacitance. The other terminal of the capacitance is coupled to a switching mechanism. The switching mechanism is set to couple the other terminal of the capacitance to a first amplifier or a second amplifier for a portion of each signal cycle thereby full-wave rectifying a transient current flowing between the two terminals in the capacitance. Outputs of the first amplifier and the second amplifier are coupled to a current measurement mechanism for measuring the current. The capacitance is determined from the measured current. Several variations on this embodiment are provided.
摘要翻译：本发明的一个实施例提供一种用于测量电容的电子电路和方法。信号发生机构在电容的一个端子上产生具有预定频率和预定义的低和高电压电平的信号。电容的另一个端子耦合到开关机构。开关机构被设置为将电容的另一个端子耦合到每个信号周期的一部分的第一放大器或第二放大器，由此对在电容中的两个端子之间流动的瞬态电流进行全波整流。第一放大器和第二放大器的输出耦合到用于测量电流的电流测量机构。电容由测量电流确定。提供了该实施例的几个变型。

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