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    • 11. 发明授权
    • Variable length image coding system
    • 可变长度图像编码系统
    • US5319457A
    • 1994-06-07
    • US942182
    • 1992-09-09
    • Tomoko NakahashiTaizo Kinoshita
    • Tomoko NakahashiTaizo Kinoshita
    • H03M7/40H03M7/42H04B14/04H04N1/413H04N7/58H04N19/00H04N7/13
    • H03M7/42H04N19/152H04N19/184H04N19/436H04N19/60H04N21/2365H04N21/4347H04N19/13H04N19/146H04N19/91
    • A variable length image coding system for multiplexing multi channel parallel data at a specified speed after making variable length coding, and capable of suppressing the variation of amount of code generated upon multiplexing to within a specified range. In order that the total output of the sub-buffer memories is suppressed to within a certain range, the bit calculator calculates the amounts of code generated from the coders of each of the variable length coder sets, selects suitable ones of the coders for the respective channels, and controls the selectors, the output time zones of data from the sub-buffer memories, and the multiplexer. The coder buffer memory reads data in synchronism with the transmission speed and controls the variable length coder sets by feedback or stops the output of data by supplying a dummy in order to prevent the overflow and underflow. Since the amount of code for each n blocks is limited, the freedom of the assignment of amount of code to each block can be increased as compared with the case of single-block unit processing.
    • 一种可变长度图像编码系统,用于在进行可变长度编码之后以特定速度多路复用多通道并行数据,并且能够将多路复用时产生的代码量的变化抑制在指定范围内。 为了使子缓冲存储器的总输出被抑制在一定范围内,位计算器计算从每个可变长度编码器组的编码器产生的代码量,为相应的编码器选择合适的编码器 通道,并控制选择器,来自子缓冲存储器的数据的输出时区和多路复用器。 编码器缓冲存储器与传输速度同步地读取数据,并通过反馈来控制可变长度编码器集合,或通过提供虚拟数据来停止数据输出,以防止溢出和下溢。 由于每个n个块的代码量受到限制,因此与单个块单元处理的情况相比,可以增加对每个块的代码量的分配的自由度。
    • 17. 发明授权
    • Threshold voltage fluctuation compensation circuit for FETS
    • FETS的阈值电压波动补偿电路
    • US4857769A
    • 1989-08-15
    • US143385
    • 1988-01-13
    • Nobuo KoteraKiichi YamashitaTaizo KinoshitaHirotoshi TanakaSatoshi TanakaMinoru Nagata
    • Nobuo KoteraKiichi YamashitaTaizo KinoshitaHirotoshi TanakaSatoshi TanakaMinoru Nagata
    • H03K19/003
    • H03K19/00384
    • This invention relates to a threshold voltage detection circuit for detecting the threshold voltage of field effect transistors (FETs) and to a semiconductor circuit capable of a stable operation irrespective of the fluctuation of the threshold voltage by utilizing this threshold voltage detection circuit. The source-drain path of first FET is connected in series with that of second FET having substantially the same threshold voltage as that of the first FET and the conductances of these first and second FETs are set to a predetermined ratio to generate a voltage drop associated with the threshold voltage in the first FET. This voltage drop can be used for detecting the threshold voltage and for level-shifting. The output of the series connection of the first and second FETs is applied to the gate of a constant current FET having the same threshold voltage as that of the first and second FETs and the drain current of the constant current FET can thus be set irrespective of the fluctuation of the threshold voltage.
    • 本发明涉及一种阈值电压检测电路,用于通过利用该阈值电压检测电路来检测场效应晶体管(FET)的阈值电压和能够稳定工作的半导体电路,而与阈值电压的波动无关。 第一FET的源极 - 漏极路径与具有与第一FET基本相同的阈值电压的第二FET的源极 - 漏极路径串联连接,并且将这些第一和第二FET的电导设置为预定的比率以产生相关的电压降 与第一FET中的阈值电压。 该电压降可用于检测阈值电压和电平转换。 第一和第二FET的串联连接的输出被施加到具有与第一和第二FET相同的阈值电压的恒流FET的栅极,因此可以设定恒定电流FET的漏极电流,而不管 阈值电压的波动。