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11. 发明授权

US07745809B1 Ultra high density phase change memory having improved emitter contacts, improved GST cell reliability and highly matched UHD GST cells using column mirco-trench strips 有权
标题翻译：具有改进的发射体触点，改善的GST电池可靠性的超高密度相变存储器以及使用柱式微通道条带的高度匹配的UHD GST电池
公开(公告)号：US07745809B1
公开(公告)日：2010-06-29
申请号：US12062444
申请日：2008-04-03
申请人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
IPC分类号： H01L29/04
CPC分类号： H01L45/1233 , H01L27/0688 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： Embodiments of the present invention provide an apparatus comprising a substrate comprising an emitter layer and at least one emitter interface adjacent to the emitter layer, and a metal protective layer on a top surface of the at least one emitter interface. A method of manufacturing such an apparatus is also disclosed. The method may include performing plasma nitridation directed at column micro-trench strips. Other embodiments are also described.
摘要翻译：本发明的实施例提供了一种装置，其包括：衬底，其包括发射极层和与发射极层相邻的至少一个发射极接口，以及在所述至少一个发射极接口的顶表面上的金属保护层。还公开了制造这种装置的方法。该方法可以包括执行针对柱状微沟槽条带的等离子体氮化。还描述了其它实施例。

12. 发明授权

US07610285B1 System and method for classifying objects 失效
标题翻译：用于分类对象的系统和方法
公开(公告)号：US07610285B1
公开(公告)日：2009-10-27
申请号：US11524831
申请日：2006-09-21
申请人： Keith Zoellner , Peter Lee , Brad Might
发明人： Keith Zoellner , Peter Lee , Brad Might
IPC分类号： G06F17/30
CPC分类号： G06F17/30705 , G06F17/30115 , G06F17/3012 , Y10S707/99937
摘要： Embodiments of a classification pipeline disclosed herein have the ability to both collect data as it occurs and dynamically redact it, allowing ongoing statistics to be gathered and maintained while simultaneously constraining the total amount of storage capacity that must be dedicated to such a purpose. Various types of information can be extracted from or obtained on the object through the classification pipeline. In one embodiment, the classification pipeline comprises a plurality of layers implemented as a set of services available to network clients through a Web interface or an Applications Programming Interface (API). Each client can subscribe to one or more layers of the classification pipeline at their leisure and tailor their classification pipeline configuration through the interface. The classification pipeline can be configured to collaborate with other software to provide a consistent snapshot of the state of a network environment based on data collected at the time.
摘要翻译：本文公开的分类流程的实施例具有在数据发生时收集数据的能力，并且动态地对其进行修改，从而允许收集和维护正在进行的统计信息，同时限制必须专用于此目的的总存储容量。可以通过分类管道从物体中提取或获取各种类型的信息。在一个实施例中，分类流水线包括通过Web接口或应用编程接口（API）来实现为可用于网络客户端的一组服务的多个层。每个客户端可以随意订阅分层管道的一层或多层，并通过接口定制其分类流水线配置。分类流水线可以配置为与其他软件协作，以便根据当时收集的数据提供网络环境状态的一致性快照。

13. 发明申请

US20080246015A1 METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT 有权
标题翻译：使用双重加热器切割形成高效GST细胞的方法
公开(公告)号：US20080246015A1
公开(公告)日：2008-10-09
申请号：US12060792
申请日：2008-04-01
申请人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
IPC分类号： H01L45/00
CPC分类号： H01L27/2463 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described.
摘要翻译：本发明的实施例提供一种方法，其包括提供包括多个单元的晶片，每个单元包括至少一个发射极。所述方法还包括在晶片的字线方向上执行平版印刷操作，以形成预热器元件布置，在跨过预热器元件布置的晶片的位线方向上执行平版印刷操作，以形成预加工元件 - 加热器元件，并且跨越预热器元件的一部分在字线方向上执行光刻操作，以形成邻近每个发射器的加热元件。还描述了其它实施例。

14. 发明申请

US20080205141A1 Circuit and method for multiple-level programming, reading, and erasing dual-sided nonvolatile memory cell 有权
标题翻译：用于多级编程，读取和擦除双面非易失性存储单元的电路和方法
公开(公告)号：US20080205141A1
公开(公告)日：2008-08-28
申请号：US12069637
申请日：2008-02-12
申请人： Peter Lee , Fu-Chang Hsu
发明人： Peter Lee , Fu-Chang Hsu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： H01L29/7887 , G11C7/18 , G11C11/5671 , G11C16/0475 , G11C16/0483 , G11C16/08 , G11C16/24 , H01L27/115 , H01L29/7923
摘要： A control apparatus programs, reads, and erases trapped charges representing multiple data bits from a charge trapping region of a NMOS dual-sided charge-trapping nonvolatile memory cell includes a programming circuit, an erasing circuit, and a reading circuit. The programming circuit provides a negative medium large program voltage to cell's gate along with positive drain and source voltage to inject hot carriers of holes to two charge trapping regions, one of a plurality of threshold adjustment voltages representing a portion of the multiple data bits to the drain and source regions to set the hot carrier charge levels to the two charge trapping regions. The erasing circuit provides a very large positive erase voltage to tunnel the electrons from cell's channel to whole trapping layer including the two charge trapping regions. The reading circuit generates one of a plurality of threshold detection voltages to detect one of a plurality of programmed threshold voltages representative of multiple data bits, generates a drain voltage level to activate the charge-trapping nonvolatile memory cell.
摘要翻译：控制装置对来自NMOS双侧电荷捕获非易失性存储单元的电荷捕获区域的多个数据位进行编程，读取和擦除捕获的电荷包括编程电路，擦除电路和读取电路。编程电路向单元的栅极提供负的中等大的编程电压以及正的漏极和源极电压，以将空穴的热载流子注入到两个电荷俘获区域，多个阈值调整电压中的一个表示多个数据位的一部分漏极和源极区域，以将热载流子电荷电平设置为两个电荷捕获区域。擦除电路提供非常大的正擦除电压，以将电子从电池的通道隧穿到包括两个电荷俘获区域的整个俘获层。读取电路产生多个阈值检测电压中的一个，以检测表示多个数据位的多个编程的阈值电压中的一个，产生漏极电压电平以激活电荷捕获非易失性存储单元。

15. 发明申请

US20080205140A1 Bit line structure for a multilevel, dual-sided nonvolatile memory cell array 审中-公开
标题翻译：用于多层双面非易失性存储单元阵列的位线结构
公开(公告)号：US20080205140A1
公开(公告)日：2008-08-28
申请号：US12069228
申请日：2008-02-08
申请人： Peter Lee , Fu-Chang Hsu
发明人： Peter Lee , Fu-Chang Hsu
IPC分类号： G11C16/04 , G11C16/06 , H01L21/336
CPC分类号： H01L29/7887 , G11C7/18 , G11C11/5671 , G11C16/0475 , G11C16/0483 , G11C16/08 , G11C16/24 , H01L27/115 , H01L29/7923
摘要： A nonvolatile memory array includes a plurality of dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping that is arranged in a NAND series string of dual-sided charge-trapping nonvolatile memory cells. Each NAND series string has a top select transistor and a bottom select transistor. A plurality of bit lines is connected in a cross connective columnar bit line structure such that each column of the dual-sided charge-trapping nonvolatile memory cells is connected to an associated pair of bit lines. The first of the associated pair of bit lines is further connected to a first adjacent column of dual-sided charge-trapping nonvolatile memory cells and the second of the associated pair of bit lines is further associated with a second adjacent column of the dual-sided charge-trapping nonvolatile memory cells.
摘要翻译：非易失性存储器阵列包括以行和列排列的多个双面电荷俘获非易失性存储单元。每列上的双面电荷捕获非易失性存储单元形成至少一个分组，其被布置在NAND串联的双面电荷捕获非易失性存储单元中。每个NAND串联串具有顶部选择晶体管和底部选择晶体管。多个位线连接在交叉连接柱状位线结构中，使得双面电荷捕获非易失性存储器单元的每一列连接到相关的一对位线。相关联的一对位线中的第一个进一步连接到双面电荷捕获非易失性存储器单元的第一相邻列，并且相关联的位线对中的第二相关联还与双面电荷捕获非易失性存储器单元的第二相邻列相关联电荷捕获非易失性存储单元。

16. 发明授权

US07271769B2 Antennas encapsulated within plastic display covers of computing devices 有权
标题翻译：封装在计算设备的塑料显示盖内的天线
公开(公告)号：US07271769B2
公开(公告)日：2007-09-18
申请号：US10946868
申请日：2004-09-22
申请人： Takeshi Asano , Shohhei Fujio , Brian Paul Gaucher , Peter Lee , Duixian Liu , Kazuo Masuda , Hideyuki Usui , Osamu Yamamoto
发明人： Takeshi Asano , Shohhei Fujio , Brian Paul Gaucher , Peter Lee , Duixian Liu , Kazuo Masuda , Hideyuki Usui , Osamu Yamamoto
IPC分类号： H01Q1/24
CPC分类号： H01Q1/2266 , G06F1/1616 , G06F1/1637 , G06F1/1698 , H01Q1/22 , H01Q1/40 , H01Q7/00 , H01Q9/16 , H01Q9/42
摘要： Antenna devices are provided comprising antenna structures encapsulated or molded into plastic covers of computing devices to enable wireless communication. For example, one or more antenna structures can be encasulated within, or molded into, a plastic display cover of a portable laptop computer. Embedded antenna designs can include various antenna types that are built using one or more wires or thin metallic strips encapsulated into plastic device covers. Insert/injection molding methods can be used to encapsulate antenna structures in plastic device covers during fabrication of the plastic device covers.
摘要翻译：提供了天线装置，其包括封装或模制成计算装置的塑料盖的天线结构以实现无线通信。例如，一个或多个天线结构可以被封装在便携式膝上型计算机的塑料显示器盖内或模制在其中。嵌入式天线设计可以包括使用一个或多个电线或薄的金属条封装在塑料器件盖中构建的各种天线类型。在塑料装置盖的制造期间，可以使用插入/注射成型方法将天线结构封装在塑料装置盖中。

17. 发明申请

US20070205156A1 Novel ion exchange porous resins for solid phase extraction and chromatography 有权
标题翻译：用于固相萃取和色谱的新型离子交换多孔树脂
公开(公告)号：US20070205156A1
公开(公告)日：2007-09-06
申请号：US11799376
申请日：2007-05-01
申请人： Peter Lee , John O'Gara
发明人： Peter Lee , John O'Gara
IPC分类号： B01D15/08
CPC分类号： B01J20/26 , B01J20/261 , B01J20/264 , B01J20/28042 , B01J20/285 , B01J20/3285 , B01J39/20 , B01J39/26 , B01J41/20 , B01J2220/54 , B01J2220/58 , B01J2220/62 , B01J2220/66 , B01J2220/82 , C08F8/24 , C08F8/32 , C08F8/36 , C08F2800/20 , G01N30/02 , B01D15/361 , C08F212/36
摘要： Embodiments of the present invention are directed to porous resins for solid phase extractions. The resins feature at least one hydrophobic component, at least one hydrophilic component and at least one ion exchange functional group. The resins exhibit superior wetting and ion exchange performance.
摘要翻译：本发明的实施方案涉及用于固相萃取的多孔树脂。该树脂具有至少一种疏水性组分，至少一种亲水组分和至少一种离子交换官能团。树脂表现出优异的润湿和离子交换性能。

18. 发明申请

US20070133341A1 Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
标题翻译：组合非易失性存储器采用统一技术与字节，页面和块写入以及同步读写操作
公开(公告)号：US20070133341A1
公开(公告)日：2007-06-14
申请号：US11633334
申请日：2006-12-04
申请人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C7/10
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/14 , G11C16/16 , G11C16/3445 , G11C2216/18 , G11C2216/22 , H01L27/11521 , H01L27/11524
摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.
摘要翻译：描述了组合EEPROM和闪存，其中包含单元，其中闪存单元的堆叠栅极晶体管与选择晶体管结合使用以形成EEPROM单元。使选择晶体管足够小，以便允许EEPROM单元适应闪存单元的位线间距，这有助于将两个存储器组合成包含两个单元的存储体。闪存单元被块擦除时，EEPROM单元被字节擦除。小选择晶体管具有小的沟道长度和宽度，其通过在CHE编程操作期间增加选择晶体管上的栅极电压和预充电位线来补偿。

19. 发明申请

US20070047302A1 Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 失效
标题翻译：新颖的单片，组合非易失性存储器允许字节，页和块写入，在单元阵列中没有干扰和分割，使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US20070047302A1
公开(公告)日：2007-03-01
申请号：US11391507
申请日：2006-03-28
申请人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
摘要翻译：非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

20. 发明申请

US20060189162A1 Adhesion improvement for low k dielectrics 有权
公开(公告)号：US20060189162A1
公开(公告)日：2006-08-24
申请号：US11405852
申请日：2006-04-18
申请人： Lihua Huang , Tzu-Fang Huang , Dian Sugiarto , Jerry Sugiarto , Li-qun Xia , Peter Lee , Hichem M'Saad , Zhenjiang Cui , Sohyun Park
发明人： Lihua Huang , Tzu-Fang Huang , Dian Sugiarto , Jerry Sugiarto , Li-qun Xia , Peter Lee , Hichem M'Saad , Zhenjiang Cui , Sohyun Park
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31633 , C23C16/02 , C23C16/325 , C23C16/401 , H01L21/02126 , H01L21/02274 , H01L21/02304 , H01L21/76801 , H01L21/7681 , H01L21/76826 , H01L21/76832
摘要： Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including introducing an organosilicon compound and an oxidizing gas at a first ratio of organosilicon compound to oxidizing gas into the processing chamber, generating a plasma of the oxidizing gas and the organosilicon compound to form an initiation layer on a barrier layer comprising at least silicon and carbon, introducing the organosilicon compound and the oxidizing gas at a second ratio of organosilicon compound to oxidizing gas greater than the first ratio into the processing chamber, and depositing a first dielectric layer adjacent the dielectric initiation layer.

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