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11. 发明授权

US07516292B2 Method for predicting and avoiding danger in execution environment 有权
标题翻译：在执行环境中预测和避免危险的方法
公开(公告)号：US07516292B2
公开(公告)日：2009-04-07
申请号：US11170217
申请日：2005-06-29
申请人： Yukihiro Kimura , Masakazu Hayashi , Katsutomo Sekiguchi
发明人： Yukihiro Kimura , Masakazu Hayashi , Katsutomo Sekiguchi
IPC分类号： G06F12/00
CPC分类号： G06F12/0253 , Y10S707/99953 , Y10S707/99957
摘要： Measurement/analysis unit in a Java virtual machine has the function of measuring data when an event of garbage collection occurs, and the function of periodically measuring data. The measurement/analysis unit analyzes the measured data and predicts a danger of a memory shortage, and predicts a danger using an algorithm depending on the type of garbage collection used by the Java virtual machine. An application server is notified of a warning of the predicted danger of a memory shortage by an analysis result notification means by an inter-process communication, or the like. The measurement/analysis unit calculates a memory capacity required to avoid the predicted danger of a memory shortage, and the calculated memory capacity is transmitted to the application server by the analysis result notification means by an inter-process communication, or the like in the same way as the warning.
摘要翻译： Java虚拟机中的测量/分析单元具有当发生垃圾回收事件时测量数据的功能，以及定期测量数据的功能。测量/分析单元分析测量数据并预测内存不足的危险，并根据Java虚拟机使用的垃圾收集类型，使用算法预测危险。通过分析结果通知装置通过进程间通信等向应用服务器通知预测的存储器不足的危险的警告。测量/分析单元计算避免预测的存储器不足的危险所需的存储器容量，并且通过分析结果通知装置通过进程间通信等将所计算的存储容量发送到应用服务器，等等方式作为警告。

12. 发明授权

US06961230B2 Capacitor, capacitor equipped semiconductor device assembly, capacitor equipped circuit substrate assembly and electronic unit including semiconductor device, capacitor and circuit substrate 失效
标题翻译：电容器，配备电容器的半导体器件组件，电容器电路基板组件和包括半导体器件，电容器和电路基板的电子单元
公开(公告)号：US06961230B2
公开(公告)日：2005-11-01
申请号：US10862562
申请日：2004-06-08
申请人： Jun Otsuka , Manabu Sato , Yukihiro Kimura
发明人： Jun Otsuka , Manabu Sato , Yukihiro Kimura
IPC分类号： H01G2/06 , H01G4/30 , H01L23/498 , H01L23/50 , H01L25/00 , H05K1/14 , H05K1/16 , H05K1/18 , H01G4/228
CPC分类号： H01G2/065 , H01G4/30 , H01L23/49822 , H01L23/49833 , H01L23/50 , H01L2224/05573 , H01L2224/13025 , H01L2224/16 , H01L2224/16235 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15174 , H01L2924/15311 , H01L2924/19103 , H05K1/141 , H05K1/162 , H05K3/4688 , H05K2201/068 , H05K2201/10378 , H01L2224/05611 , H01L2924/00014 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05684
摘要： A capacitor includes a capacitor main body having a front surface on which a semiconductor device is to be mounted and a rear surface at which the capacitor main body is to be mounted on a first main surface of a circuit substrate, a plurality of internal electrodes disposed within the capacitor main body, and a plurality of via conductors penetrating the capacitor main body between the front surface and the rear surface and electrically connected to the internal electrodes, wherein the capacitor main body has a first dielectric layer located on a side of the capacitor main body closer to the front surface and a second dielectric layer located on a side of the first dielectric layer closer to the rear surface, the second dielectric layer having a higher thermal expansion coefficient and a higher dielectric constant than the first dielectric layer.
摘要翻译：电容器包括电容器主体，其具有要安装半导体器件的前表面和将电容器主体安装在电路基板的第一主表面上的后表面，多个内部电极设置电容器主体内的多个通孔导体以及贯穿电容器主体的前表面与背面之间并与内部电极电连接的多个通路导体，其中，电容器主体具有位于电容器侧的第一电介质层主体靠近前表面，第二电介质层位于第一电介质层的靠近背面的一侧，第二电介质层具有比第一电介质层更高的热膨胀系数和更高的介电常数。

13. 发明授权

US06249082B1 Electrode plate having transparent type or reflective type multi-layered conductive film and method for manufacturing the same 失效
标题翻译：具有透明型或反射型多层导电膜的电极板及其制造方法
公开(公告)号：US06249082B1
公开(公告)日：2001-06-19
申请号：US09228644
申请日：1999-01-12
申请人： Kenzo Fukuyoshi , Yukihiro Kimura , Koji Imayoshi
发明人： Kenzo Fukuyoshi , Yukihiro Kimura , Koji Imayoshi
IPC分类号： G02F11343
CPC分类号： G02F1/13439 , G02F2203/01 , G02F2203/02 , Y10T428/2958 , Y10T428/2991
摘要： An electrode plate for display device includes a substrate and a multi-layered conductive film. The multi-layered conductive film includes a lower side amorphous oxide layer, a silver-based layer, and an upper side amorphous oxide layer. The lower side amorphous oxide layer and the upper side amorphous oxide layer are formed of an amorphous and amorphous-like material. The film thickness of the upper side amorphous oxide layer is not larger than 20 nm.
摘要翻译：用于显示装置的电极板包括基板和多层导电膜。多层导电膜包括下侧无定形氧化物层，银基层和上侧无定形氧化物层。下侧无定形氧化物层和上侧无定形氧化物层由无定形和非晶态材料形成。上侧无定形氧化物层的膜厚不大于20nm。

14. 发明授权

US06214445B1 Printed wiring board, core substrate, and method for fabricating the core substrate 失效
标题翻译：印刷电路板，芯基板和芯基板的制造方法
公开(公告)号：US06214445B1
公开(公告)日：2001-04-10
申请号：US09459881
申请日：1999-12-14
申请人： Rokuro Kanbe , Yukihiro Kimura , Kouki Ogawa
发明人： Rokuro Kanbe , Yukihiro Kimura , Kouki Ogawa
IPC分类号： B32B300
CPC分类号： H05K1/162 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L23/50 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K3/429 , H05K3/4602 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K2201/0209 , H05K2201/09309 , H05K2201/09536 , H05K2201/096 , Y10T428/24917 , Y10T428/24926 , H01L2924/00
摘要： A printed wiring board includes a core substrate, one or more insulating resin layers laminated on at least one side of the core substrate, and a wiring layer formed at least between the core substrate and the insulating resin layer or between the insulating resin layers. The core substrate includes a composite dielectric layer that contains resin and a high-permittivity powder, and a plurality of metal layers disposed such that the composite dielectric layer is sandwiched therebetween. The composite dielectric layer and the metal layers constitute a laminated capacitor.
摘要翻译：印刷电路板包括芯基板，层叠在芯基板的至少一侧上的一个或多个绝缘树脂层，以及至少在芯基板和绝缘树脂层之间或绝缘树脂层之间形成的布线层。芯基板包括含有树脂和高电容率粉末的复合电介质层，并且多个金属层被布置成使得复合介电层夹在其间。复合电介质层和金属层构成叠层电容器。

15. 发明授权

US5286926A Integrated circuit package and process for producing same 失效
标题翻译：集成电路封装及其制造方法
公开(公告)号：US5286926A
公开(公告)日：1994-02-15
申请号：US868568
申请日：1992-04-15
申请人： Yukihiro Kimura , Nobuhiko Miyawaki , Masao Kuroda
发明人： Yukihiro Kimura , Nobuhiko Miyawaki , Masao Kuroda
IPC分类号： H01L23/12 , H01L23/14 , H01L23/498 , H05K1/00
CPC分类号： H01L23/49827 , H01L2223/6622 , H01L2224/16 , H01L2924/01078 , H01L2924/09701 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025
摘要： The present integrated circuit package provides both a high density of conductor poles, and reduced crosstalk noise between the conductor poles. The conductor poles are arranged within a selected number of holes in an insulating substrate. Metallized layers for shielding the conductor poles are provided on the walls of the holes in the insulating substrate which receive the conductor poles. In addition, an insulating layer is provided on the inner circumferences of the metallized layers, which insulating layers directly surround the conductor poles to preclude direct contact between the conductor poles and the metallized layers.
摘要翻译：本集成电路封装提供高密度的导体极，并减少导体极之间的串扰噪声。导体极被布置在绝缘基板中的选定数量的孔内。用于屏蔽导体极的金属化层设置在接收导体极的绝缘基板中的孔的壁上。此外，绝缘层设置在金属化层的内周上，这些绝缘层直接围绕导体极，以防止导体极与金属化层之间的直接接触。

16. 发明申请

US20050263867A1 INTERMEDIATE SUBSTRATE 有权
标题翻译：中间基板
公开(公告)号：US20050263867A1
公开(公告)日：2005-12-01
申请号：US11127192
申请日：2005-05-12
申请人： Rokuro Kambe , Tetsuya Kasiwagi , Yukihiro Kimura , Yasuhiro Sugimoto , Kazuhiro Suzuki
发明人： Rokuro Kambe , Tetsuya Kasiwagi , Yukihiro Kimura , Yasuhiro Sugimoto , Kazuhiro Suzuki
IPC分类号： H01F5/00 , H01L23/02 , H01L23/12 , H01L23/498 , H01L23/50 , H05K1/11 , H05K3/46
CPC分类号： H01L23/50 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2924/00014 , H01L2924/01012 , H01L2924/01019 , H01L2924/01025 , H01L2924/01078 , H01L2924/09701 , H01L2924/15174 , H01L2924/15311 , H01L2924/3011 , H05K1/112 , H05K3/4602 , H05K3/4694 , H05K2201/0187 , H05K2201/10674 , H01L2224/05599
摘要： An intermediate substrate is provided which reduces the effect of the difference in the coefficients of linear expansion between the terminals of the substrate and those of a semiconductor integrated circuit device, and which thus lowers the likelihood of disconnection due to thermal stress. The intermediate substrate, which is a planar member made of a polymeric material, includes a substrate core including a main core body having formed therein a sub-core compartment, and a ceramic sub-core section accommodated in the compartment. A first terminal array on the first principal surface side includes two types of terminals, functioning either as power source terminals or ground terminals, and a signal terminal. The array occupies an area entirely included within an orthogonally projected region of the sub-core section projected onto a reference plane parallel to the planar surface of the substrate core.
摘要翻译：提供了一种中间衬底，其减小了衬底的端子与半导体集成电路器件的端子之间的线性膨胀系数的差异的影响，从而降低了由于热应力引起的断开的可能性。作为由聚合物材料制成的平面构件的中间基板包括：基材芯，其包括形成有副芯隔室的主芯体和容纳在隔室中的陶瓷副芯部。第一主表面侧的第一端子阵列包括用作电源端子或接地端子的两种类型的端子和信号端子。阵列占据完全包括在子芯部分的正交投影区域内的区域，该区域投影到平行于衬底芯的平面表面的参考平面上。

17. 发明申请

US20050240641A1 Method for predicting and avoiding danger in execution environment 有权
标题翻译：在执行环境中预测和避免危险的方法
公开(公告)号：US20050240641A1
公开(公告)日：2005-10-27
申请号：US11170217
申请日：2005-06-29
申请人： Yukihiro Kimura , Masakazu Hayashi , Katsutomo Sekiguchi
发明人： Yukihiro Kimura , Masakazu Hayashi , Katsutomo Sekiguchi
IPC分类号： G06F12/02 , G06F17/30
CPC分类号： G06F12/0253 , Y10S707/99953 , Y10S707/99957
摘要： Measurement/analysis unit in a Java virtual machine has the function of measuring data when an event of garbage collection occurs, and the function of periodically measuring data. The measurement/analysis unit analyzes the measured data and predicts a danger of a memory shortage, and predicts a danger using an algorithm depending on the type of garbage collection used by the Java virtual machine. An application server is notified of a warning of the predicted danger of a memory shortage by an analysis result notification means by an inter-process communication, or the like. The measurement/analysis unit calculates a memory capacity required to avoid the predicted danger of a memory shortage, and the calculated memory capacity is transmitted to the application server by the analysis result notification means by an inter-process communication, or the like in the same way as the warning.
摘要翻译： Java虚拟机中的测量/分析单元具有当发生垃圾回收事件时测量数据的功能，以及定期测量数据的功能。测量/分析单元分析测量数据并预测内存不足的危险，并根据Java虚拟机使用的垃圾收集类型，使用算法预测危险。通过分析结果通知装置通过进程间通信等向应用服务器通知预测的存储器不足的危险的警告。测量/分析单元计算避免预测的存储器不足的危险所需的存储器容量，并且通过分析结果通知装置通过进程间通信等将所计算的存储容量发送到应用服务器，等等方式作为警告。

18. 发明授权

US06660944B1 Circuit board having solder bumps 失效
标题翻译：具有焊锡凸块的电路板
公开(公告)号：US06660944B1
公开(公告)日：2003-12-09
申请号：US08825400
申请日：1997-03-28
申请人： Haruhiko Murata , Yukihiro Kimura , Masashi Inaishi
发明人： Haruhiko Murata , Yukihiro Kimura , Masashi Inaishi
IPC分类号： H01R1204
CPC分类号： H05K3/3457 , H01L21/4853 , H01L2924/3511 , H05K3/3484 , H05K2203/0278 , H05K2203/043
摘要： A circuit board having a plurality of solder bumps is provided. The solder bumps are flattened and leveled at the tops so that the coplanarity of the solder bumps is 0.5 &mgr;m or less per 1 mm. The flattened and leveled tops of the solder bumps are formed by cold pressing, hot pressing or grinding. Method of forming such solder bumps and jigs used for carrying out such methods are also provided.
摘要翻译：提供具有多个焊锡凸块的电路板。焊料凸起在顶部变平且平整，使得焊料凸块的共面性每1mm为0.5μm或更小。焊料凸块的扁平和平整的顶部通过冷压，热压或研磨形成。还提供了形成用于执行这种方法的焊料凸块和夹具的方法。

19. 发明授权

US06333857B1 Printing wiring board, core substrate, and method for fabricating the core substrate 失效
标题翻译：印刷线路板，芯基板以及芯基板的制造方法
公开(公告)号：US06333857B1
公开(公告)日：2001-12-25
申请号：US09556790
申请日：2000-04-25
申请人： Rokuro Kanbe , Yukihiro Kimura , Kouki Ogawa
发明人： Rokuro Kanbe , Yukihiro Kimura , Kouki Ogawa
IPC分类号： H05K111
CPC分类号： H05K1/162 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L23/50 , H01L2224/16 , H01L2924/01025 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/3011 , H05K2201/0209 , H05K2201/09536
摘要： A printed wiring board includes a core substrate including a laminated capacitor. The laminated capacitor includes a plurality of composite dielectric layers and a plurality of metal layers stacked alternately. Three types through-hole conductors are provided which extend between the upper and lower surfaces of the core substrate. The first through-hole conductors are directly connected to first metal layers serving one electrode of the laminated capacitor, the second through-hole conductors are directly connected to second metal layers serving the other electrode of the laminated capacitor, and the third through-hole conductors are not connected to any of the first and second metal layers. The first and second through-hole conductors are used for establishing electrical connections between power supply and ground lines and an IC chip mounted on the printed wiring board. The third through-hole conductor is used as a signal line. Since the laminated capacitor is connected between the first and second through-hole conductors, noise entry is effectively prevented.
摘要翻译：印刷电路板包括具有叠层电容器的芯基板。层叠电容器包括多个复合电介质层和交替堆叠的多个金属层。提供三个类型的通孔导体，其在芯基板的上表面和下表面之间延伸。第一通孔导体直接连接到用于层叠电容器的一个电极的第一金属层，第二通孔导体直接连接到用于叠层电容器的另一个电极的第二金属层，第三通孔导体不连接到第一和第二金属层中的任何一个。第一和第二通孔导体用于建立电源和地线之间的电连接以及安装在印刷电路板上的IC芯片。第三通孔导体用作信号线。由于层叠电容器连接在第一和第二通孔导体之间，因此有效地防止噪声进入。

20. 发明授权

US5293502A Integrated circuit package 失效
标题翻译：集成电路封装
公开(公告)号：US5293502A
公开(公告)日：1994-03-08
申请号：US868567
申请日：1992-04-15
申请人： Yukihiro Kimura , Nobuhiko Miyawaki , Masao Kuroda
发明人： Yukihiro Kimura , Nobuhiko Miyawaki , Masao Kuroda
IPC分类号： H01L23/13 , H01L21/48 , H01L23/12 , H01L23/14 , H01L23/498 , H05K01/00
CPC分类号： H01L23/49827 , H01L21/486 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025
摘要： The present integrated circuit package provides both a high density of conductor poles, and reduced crosstalk noises between the conductor poles. The conductor poles are received within holes in an insulating substrate. The insulating substrate has a laminated, multi-layer ceramic substrate structure comprising insulating plates having metallized layers thereon which constitute a portion of the walls of the holes. In addition, insulating layers for insulating the metallized layers from the conductor poles are formed within a selected number of the holes.
摘要翻译：本集成电路封装既提供高导体极的高密度，又减少导体极之间的串扰噪声。导体极接收在绝缘基板的孔内。绝缘基板具有层叠的多层陶瓷基板结构，其包括在其上形成有金属化层的绝缘板，其构成孔的壁的一部分。此外，在选定数量的孔内形成用于使金属化层与导体极绝缘的绝缘层。

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