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1. 发明授权

US06214445B1 Printed wiring board, core substrate, and method for fabricating the core substrate 失效
标题翻译：印刷电路板，芯基板和芯基板的制造方法
公开(公告)号：US06214445B1
公开(公告)日：2001-04-10
申请号：US09459881
申请日：1999-12-14
申请人： Rokuro Kanbe , Yukihiro Kimura , Kouki Ogawa
发明人： Rokuro Kanbe , Yukihiro Kimura , Kouki Ogawa
IPC分类号： B32B300
CPC分类号： H05K1/162 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L23/50 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K3/429 , H05K3/4602 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K2201/0209 , H05K2201/09309 , H05K2201/09536 , H05K2201/096 , Y10T428/24917 , Y10T428/24926 , H01L2924/00
摘要： A printed wiring board includes a core substrate, one or more insulating resin layers laminated on at least one side of the core substrate, and a wiring layer formed at least between the core substrate and the insulating resin layer or between the insulating resin layers. The core substrate includes a composite dielectric layer that contains resin and a high-permittivity powder, and a plurality of metal layers disposed such that the composite dielectric layer is sandwiched therebetween. The composite dielectric layer and the metal layers constitute a laminated capacitor.
摘要翻译：印刷电路板包括芯基板，层叠在芯基板的至少一侧上的一个或多个绝缘树脂层，以及至少在芯基板和绝缘树脂层之间或绝缘树脂层之间形成的布线层。芯基板包括含有树脂和高电容率粉末的复合电介质层，并且多个金属层被布置成使得复合介电层夹在其间。复合电介质层和金属层构成叠层电容器。

2. 发明授权

US06333857B1 Printing wiring board, core substrate, and method for fabricating the core substrate 失效
标题翻译：印刷线路板，芯基板以及芯基板的制造方法
公开(公告)号：US06333857B1
公开(公告)日：2001-12-25
申请号：US09556790
申请日：2000-04-25
申请人： Rokuro Kanbe , Yukihiro Kimura , Kouki Ogawa
发明人： Rokuro Kanbe , Yukihiro Kimura , Kouki Ogawa
IPC分类号： H05K111
CPC分类号： H05K1/162 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L23/50 , H01L2224/16 , H01L2924/01025 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/3011 , H05K2201/0209 , H05K2201/09536
摘要： A printed wiring board includes a core substrate including a laminated capacitor. The laminated capacitor includes a plurality of composite dielectric layers and a plurality of metal layers stacked alternately. Three types through-hole conductors are provided which extend between the upper and lower surfaces of the core substrate. The first through-hole conductors are directly connected to first metal layers serving one electrode of the laminated capacitor, the second through-hole conductors are directly connected to second metal layers serving the other electrode of the laminated capacitor, and the third through-hole conductors are not connected to any of the first and second metal layers. The first and second through-hole conductors are used for establishing electrical connections between power supply and ground lines and an IC chip mounted on the printed wiring board. The third through-hole conductor is used as a signal line. Since the laminated capacitor is connected between the first and second through-hole conductors, noise entry is effectively prevented.
摘要翻译：印刷电路板包括具有叠层电容器的芯基板。层叠电容器包括多个复合电介质层和交替堆叠的多个金属层。提供三个类型的通孔导体，其在芯基板的上表面和下表面之间延伸。第一通孔导体直接连接到用于层叠电容器的一个电极的第一金属层，第二通孔导体直接连接到用于叠层电容器的另一个电极的第二金属层，第三通孔导体不连接到第一和第二金属层中的任何一个。第一和第二通孔导体用于建立电源和地线之间的电连接以及安装在印刷电路板上的IC芯片。第三通孔导体用作信号线。由于层叠电容器连接在第一和第二通孔导体之间，因此有效地防止噪声进入。

3. 发明授权

US5093186A Multilayer ceramic wiring board 失效
标题翻译：多层陶瓷接线板
公开(公告)号：US5093186A
公开(公告)日：1992-03-03
申请号：US584641
申请日：1990-09-19
申请人： Yukihiro Kimura , Nobuhiko Miyawaki , Sumihito Tominaga , Rokuro Kanbe
发明人： Yukihiro Kimura , Nobuhiko Miyawaki , Sumihito Tominaga , Rokuro Kanbe
IPC分类号： H05K3/46 , H05K1/02 , H05K1/03 , H05K1/09 , H05K3/40
CPC分类号： H05K1/0271 , H05K3/4061 , H05K1/0306 , H05K1/092 , H05K2201/0269 , H05K2201/068 , H05K3/4611 , H05K3/4629 , Y10S428/901 , Y10T428/24917
摘要： A multilayer ceramic wiring board including a ceramic board having a plurality of through-holes and formed by laminating three or more green sheets of a ceramic material and burning a laminate of the green sheets, and a plurality of conductors provided in the through-holes. Each of the conductors is formed of a ceramic material and a conductive material in combination. The ceramic board is composed of a pair of upper and lower layer portions each having at least an outermost surface layer and an inner layer portion disposed between the upper and lower portions. The conductors are composed of an outer conductor portion formed in the upper and lower layer portions and an inner conductor portion formed in the inner layer portion. The outer conductor portion has a content ratio of the ceramic material higher than that of the inner conductor portion. Accordingly, the generation of cracks in the outer conductor portion disposed at the upper and lower layer portions of the ceramic board can be prevented, and an electric resistance can be reduced.
摘要翻译：一种多层陶瓷布线板，包括具有多个通孔的陶瓷板，并且通过层叠三种或更多种陶瓷材料的生片并烧制生片的层压体，以及设置在通孔中的多个导体。每个导体由陶瓷材料和导电材料组合形成。陶瓷板由一对上下层部分组成，每一层至少具有最外表面层和设置在上部和下部之间的内层部分。导体由形成在上层部和下层部中的外部导体部和形成在内层部的内部导体部构成。外导体部分的陶瓷材料的含量比高于内导体部分的含量比。因此，可以防止在布置在陶瓷板的上层和下层部分的外导体部分中产生裂纹，并且可以降低电阻。

4. 发明授权

US5250244A Method of producing sintered ceramic body 失效
标题翻译：烧结陶瓷体的制造方法
公开(公告)号：US5250244A
公开(公告)日：1993-10-05
申请号：US911782
申请日：1992-07-10
申请人： Yukihiro Kimura , Sumihito Tominaga , Rokuro Kanbe
发明人： Yukihiro Kimura , Sumihito Tominaga , Rokuro Kanbe
IPC分类号： C04B35/111 , C04B35/185 , C04B35/622 , C04B35/64
CPC分类号： C04B35/622 , C04B35/111 , C04B35/185
摘要： A method of producing a sintered body by molding a mixture of a ceramic base powder, a sintering assistant powder and an organic binder and sintering the molded body in a non-oxidizing atmosphere is disclosed in which the ceramic base powder has such a particle size distribution that the amount of powder particles not greater than 1.0 .mu.m in size is not more than 15% by weight and the average particle diameter is not greater than 5 .mu.m. According to the method, therefore, sufficient passage of gas is secured in a degreasing step, resulting in an enhanced degreasing efficiency and exellent sintering properties. Where the sintering assistant powder has such a particle size distribution that the amount of powder particles not greater than 10 .mu.m in size is not more than 5% by weight, the amount of coarse powder is extremely small and, therefore, large voids are not formed. It is thus possible to produce easily a high-quality sintered body by controlling the respective particle size distributions of the powders.
摘要翻译：公开了一种通过模制陶瓷基底粉末，烧结辅助粉末和有机粘合剂的混合物并在非氧化性气氛中烧结成型体来制造烧结体的方法，其中陶瓷基础粉末具有这样的粒度分布不大于1.0μm的粉末颗粒的量不大于15重量％，平均粒径不大于5μm。因此，根据该方法，在脱脂工序中确保充分的气体通过，从而提高脱脂效率和良好的烧结性能。当烧结辅助粉末具有这样的粒度分布，其尺寸不大于10微米的粉末颗粒的量不大于5重量％时，粗粉末的量非常小，因此，大的空隙不是形成。因此，通过控制粉末的各自的粒度分布，可以容易地制造高品质的烧结体。

5. 发明授权

US5468997A Integrated circuit package having a multilayered wiring portion formed on an insulating substrate 失效
标题翻译：集成电路封装，其具有形成在绝缘基板上的多层布线部
公开(公告)号：US5468997A
公开(公告)日：1995-11-21
申请号：US368384
申请日：1994-12-30
申请人： Ryuji Imai , Rokuro Kanbe
发明人： Ryuji Imai , Rokuro Kanbe
IPC分类号： H01L23/538 , H01L23/522 , H01L23/48 , H01L29/41
CPC分类号： H01L23/5383 , H01L23/5385 , H01L2224/48091 , H01L2224/48227 , H01L24/48 , H01L2924/00014 , H01L2924/14 , H01L2924/16152
摘要： An integrated circuit package in which three conductor columns for connecting an insulating substrate and an integrated circuit are connected in parallel for use as I/O vias. Thereby, the conductor columns in a multilayer wiring portion between an integrated circuit and an insulating substrate is prevented from disconnecting.
摘要翻译：用于连接绝缘基板和集成电路的三个导体柱并联连接用作I / O通孔的集成电路封装。由此，防止集成电路和绝缘基板之间的多层布线部分中的导体柱断开。

6. 发明授权

US4532190A Metal-ceramics composite materials 失效
标题翻译：金属陶瓷复合材料
公开(公告)号：US4532190A
公开(公告)日：1985-07-30
申请号：US535050
申请日：1983-09-23
申请人： Rokuro Kanbe , Kazuo Kimura
发明人： Rokuro Kanbe , Kazuo Kimura
IPC分类号： B23K1/20 , C04B37/02 , C04B41/52 , C04B41/90 , B32B15/04
CPC分类号： C04B35/645 , C04B37/026 , C04B41/52 , C04B2237/122 , C04B2237/124 , C04B2237/125 , C04B2237/343 , C04B2237/348 , C04B2237/365 , C04B2237/368 , C04B2237/407 , C04B2237/408 , C04B2237/708 , C04B2237/72 , Y10T428/12576 , Y10T428/12611 , Y10T428/12806 , Y10T428/12812 , Y10T428/12826 , Y10T428/12882 , Y10T428/12903 , Y10T428/1291
摘要： A metal-ceramics composite material is produced by forming a metal film comprised of three layers on a ceramic substrate, and laminating a metal member thereon, the metal film comprising first layer of Group IV a metal, second layer of Group VIa metal and third layer of Group Ib metal, wherein the first and second layers are formed by gas deposition technique and the Group Ib layer may be formed by gas deposition technique or electrochemical plating. An additional Group VIII metal layer may be interposed between Group VIa layer and Group Ib layer by gas deposition technique.
摘要翻译：金属陶瓷复合材料通过在陶瓷基板上形成由三层构成的金属膜，并在其上层叠金属构件而制造金属膜，该金属膜包括第IV族金属，第Ⅵa族金属的第二层和第三层的Ib族金属，其中第一和第二层通过气体沉积技术形成，并且Ib族层可以通过气相沉积技术或电化学电镀形成。可以通过气体沉积技术将另外的VIII族金属层插入VIa族组和Ib族组之间。

7. 发明授权

US5721453A Integrated circuit package 失效
标题翻译：集成电路封装
公开(公告)号：US5721453A
公开(公告)日：1998-02-24
申请号：US895990
申请日：1992-06-08
申请人： Ryuji Imai , Rokuro Kanbe
发明人： Ryuji Imai , Rokuro Kanbe
IPC分类号： H01L23/12 , H01L23/538 , H05K1/11 , H05K3/46 , H01L23/053
CPC分类号： H01L23/5383 , H01L2924/0002 , H05K1/115
摘要： An integrated circuit package comprises a power supply conductor film having a potential and conductor columns insulated from and passed through the power supply conductor film. A power supply conductor column comprises one of the conductor columns connected to a power supply having a potential different from the power supply conductor film. The other conductor columns are signal conductor columns for exchanging signals with mounted integrated circuits. An insulation space between the power supply conductor film and the power supply conductor column is greater than an insulation space between the power supply conductor film and a signal conductor column. Thereby, a probability of short-circuit occurrence in the power supply conductor film across the power supply conductor column is lowered.
摘要翻译：集成电路封装包括具有与电源导体膜绝缘并通过电源导体膜的电位和导体柱的电源导体膜。电源导体柱包括连接到具有不同于电源导体膜的电位的电源的导体列中的一个。其他导体列是用于与安装的集成电路交换信号的信号导体列。电源导体膜和电源导体柱之间的绝缘空间大于电源导体膜和信号导体柱之间的绝缘空间。由此，供电导体柱的电源导体膜的短路发生的概率降低。

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