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11. 发明授权

US07043417B1 High speed software driven emulator comprised of a plurality of emulation processors with improved multiplexed data memory 有权
标题翻译：由具有改进的多路复用数据存储器的多个仿真处理器组成的高速软件驱动的仿真器
公开(公告)号：US07043417B1
公开(公告)日：2006-05-09
申请号：US09656146
申请日：2000-09-06
申请人： William F. Beausoleil , R. Bryan Cook , Tak-kwong Ng , Helmut Roth , Peter Tannenbaum , Lawrence A. Thomas , Norton J. Tomassetti
发明人： William F. Beausoleil , R. Bryan Cook , Tak-kwong Ng , Helmut Roth , Peter Tannenbaum , Lawrence A. Thomas , Norton J. Tomassetti
IPC分类号： G06F9/455 , G06F13/00
CPC分类号： G06F13/1647
摘要： In an emulator processor cluster, the read ports of a shared input and data memory stack are time multiplexed to serve more than one processor. In an exemplary embodiment of the invention, a 256×8 memory array serves as the shared memory for four processors in a cluster. Two read ports are time multiplexed among the four processors in the cluster. On one read cycle, data from the two read ports is coupled to two processors. The next read cycle reads data from the same two ports to the remaining two processors. In the preferred embodiment, the memory operates at twice the system clock speed so that overall emulation process execution time is not effected.
摘要翻译：在仿真器处理器集群中，共享输入和数据存储器堆栈的读取端口被时间复用以服务于多个处理器。在本发明的示例性实施例中，256x8存储器阵列用作簇中四个处理器的共享存储器。两个读端口在集群中的四个处理器之间进行时间复用。在一个读取周期中，来自两个读取端口的数据耦合到两个处理器。下一个读取周期将数据从相同的两个端口读取到剩余的两个处理器。在优选实施例中，存储器以系统时钟速度的两倍运行，使得整体仿真处理执行时间不受影响。

12. 发明授权

US06774475B2 Vertically stacked memory chips in FBGA packages 失效
标题翻译： FBGA封装中垂直堆叠的存储芯片
公开(公告)号：US06774475B2
公开(公告)日：2004-08-10
申请号：US10056256
申请日：2002-01-24
申请人： Edmund D. Blackshear , William F. Beausoleil , N. James Tomassetti
发明人： Edmund D. Blackshear , William F. Beausoleil , N. James Tomassetti
IPC分类号： H01L2302
CPC分类号： G11C5/04 , H01L24/73 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2225/1005 , H01L2225/107 , H01L2225/1094 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H05K1/144 , H01L2924/00 , H01L2924/00012
摘要： A method and structure for a memory structure that includes a plurality of substrates stacked one on another is disclosed. The invention includes a plurality of connectors connecting the substrates to one another and a plurality of memory chip packages mounted on the substrates. The connectors have a size sufficient to form a gap between the substrates. The gap is larger than a height of the memory chip packages.
摘要翻译：公开了一种包括多个彼此层叠的基板的存储器结构的方法和结构。本发明包括将基板彼此连接的多个连接器和安装在基板上的多个存储芯片封装。连接器具有足以在基板之间形成间隙的尺寸。该间隙大于存储芯片封装的高度。

13. 发明授权

US06469375B2 High bandwidth 3D memory packaging technique 失效
标题翻译：高带宽3D内存封装技术
公开(公告)号：US06469375B2
公开(公告)日：2002-10-22
申请号：US09796055
申请日：2001-02-28
申请人： William F. Beausoleil , Edmund D. Blackshear , Michael J. Ellsworth, Jr. , William F. Shutler , Norton J. Tomassetti
发明人： William F. Beausoleil , Edmund D. Blackshear , Michael J. Ellsworth, Jr. , William F. Shutler , Norton J. Tomassetti
IPC分类号： H01L2302
CPC分类号： H01L23/5385 , H01L23/5384 , H01L25/0652 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional memory module in a repetitively used pedestal connector provides signal paths unique and common to the module at its level and signal paths from the level below unique to and common to modules at levels above. In order to provide a unique signal path from a substrate to each memory module, while using identical pedestal connectors at each level, signal lines are skewed from where they enter the bottom surface of the pedestal connector to where they exit the top surface. For example, each input in a line of inputs is connected to a matching line of outputs, but with a shift of one position between input and output.
摘要翻译：重复使用的基座连接器中的三维存储器模块提供了模块在其级别上独特且通用的信号路径，以及从级别以下的模块的独特级别和通用级别的信号路径。为了提供从衬底到每个存储器模块的独特的信号路径，同时在每个级别使用相同的基座连接器，信号线从它们进入基座连接器的底表面到它们离开顶表面的地方偏斜。例如，一行输入中的每个输入连接到匹配的输出行，但是在输入和输出之间移动一个位置。

14. 发明授权

US07725304B1 Method and apparatus for coupling data between discrete processor based emulation integrated chips 有权
标题翻译：用于在基于离散处理器的仿真集成芯片之间耦合数据的方法和装置
公开(公告)号：US07725304B1
公开(公告)日：2010-05-25
申请号：US11438628
申请日：2006-05-22
申请人： William F. Beausoleil , Beshara G. Elmufdi
发明人： William F. Beausoleil , Beshara G. Elmufdi
IPC分类号： G06F9/455
CPC分类号： G06F17/5027
摘要： A method and apparatus for coupling data between discrete processor-based emulation chips is described. The apparatus is a processor-based hardware emulation integrated circuits (chips) element comprising a plurality of discrete hardware emulation chips, each emulation chip coupled to another emulation chip by a crossbar for coupling data between the plurality of chips. The method comprises providing data to a crossbar from a first discrete emulation chip, selecting the data from the crossbar using a discrete second emulation chip, and storing the data in a data array in the second discrete emulation chip.
摘要翻译：描述了用于在基于分立处理器的仿真芯片之间耦合数据的方法和装置。该装置是包括多个离散硬件仿真芯片的基于处理器的硬件仿真集成电路（芯片）元件，每个仿真芯片由交叉开关耦合到另一仿真芯片，用于在多个芯片之间耦合数据。该方法包括从第一离散仿真芯片向交叉开关提供数据，使用离散的第二仿真芯片从交叉开关中选择数据，以及将数据存储在第二离散仿真芯片中的数据阵列中。

15. 发明授权

US5551013A Multiprocessor for hardware emulation 失效
标题翻译：用于硬件仿真的多处理器
公开(公告)号：US5551013A
公开(公告)日：1996-08-27
申请号：US253881
申请日：1994-06-03
申请人： William F. Beausoleil , Tak-Kwong Ng , Harold R. Palmer
发明人： William F. Beausoleil , Tak-Kwong Ng , Harold R. Palmer
IPC分类号： G06F11/22 , G06F17/50 , G06F9/455
CPC分类号： G06F17/5027
摘要： A software-driven multiprocessor emulation system comprising a plurality of emulation processors connected in parallel in a module. One or more modules of processors comprise an emulation system. An execution unit in each processor includes a table-lookup unit for emulating any type of logic gate function. A parallel bus connects an output of each processor to a multiplexor input with every other processor in a module. Each processor embeds a control store to store software logic-representing signals for controlling operations of each processor. Also a data store is embedded in each processor to receive data generated under control of the software signals in the control store. The parallel processors on each module have a module input and a module output from each processor. The plurality of modules have their module outputs inter-connected to module inputs of all other modules. A sequencer synchronously cycles the processors through mini-cycles on all modules. Logic software drives all of the processors in the emulation system to emulate a complex array of Boolean logic, which may be all of the logic gates in a complex logic semiconductor chip. Special control means associated with the embedded control store and the embedded data store in each of the processors enables them to emulate all or part of a memory array within a target logic entity being emulated by the multiprocessor emulation system. Each cycle of processing may control the emulation of a level of logic being verified by the emulation processor.
摘要翻译：一种软件驱动的多处理器仿真系统，包括在模块中并联连接的多个仿真处理器。处理器的一个或多个模块包括仿真系统。每个处理器中的执行单元包括用于模拟任何类型的逻辑门功能的表查找单元。并行总线将每个处理器的输出与模块中的每个其他处理器连接到多路复用器输入。每个处理器嵌入控制存储器以存储用于控制每个处理器的操作的逻辑代表信号的软件。另外，在每个处理器中嵌入数据存储器以接收在控制存储器中的软件信号的控制下生成的数据。每个模块上的并行处理器具有模块输入和每个处理器的模块输出。多个模块的模块输出与所有其他模块的模块输入相互连接。定序器通过所有模块上的微循环同步循环处理器。逻辑软件驱动仿真系统中的所有处理器来仿真一个复杂的布尔逻辑阵列，它可能是复杂逻辑半导体芯片中的所有逻辑门。与嵌入式控制存储器相关联的特殊控制装置和每个处理器中的嵌入式数据存储器使得它们能够模拟由多处理器仿真系统仿真的目标逻辑实体内的存储器阵列的全部或部分。每个处理循环可以控制由仿真处理器验证的逻辑电平的仿真。

16. 发明授权

US5109496A Most recently used address translation system with least recently used (LRU) replacement 失效
标题翻译：最近使用的最近使用的地址转换系统（LRU）替换
公开(公告)号：US5109496A
公开(公告)日：1992-04-28
申请号：US413408
申请日：1989-09-27
申请人： William F. Beausoleil , Tak-Kwong Ng
发明人： William F. Beausoleil , Tak-Kwong Ng
IPC分类号： G06F12/10 , G06F12/12
CPC分类号： G06F12/123 , G06F12/1027
摘要： A least recently used associative map is described for translating virtual memory addresses to real memory addresses. The map includes a stack of storage devices each with a comparator. The storage devices are arranged in a push down stack with an input storage device to receive the incoming virtual address and store the corresponding real address and the other storage devices coupled to the output of the previous higher storage devices and with storage devices storing the translation of virtual address and real address in order of recent use with the last or bottom storage device storing the least recently used device. When the comparator detects a compare that real address is provided out and that translation is applied to the input storage device as the most recently used translation and the other translations are shifted down the stack to replace in the storage device that had the compare with the translation from the previous storage device. If there is not a compare a new translation is entered at the input storage device and the other translations are shifted down with the least recently used being shifted out if all the storage devices are full.
摘要翻译：描述了用于将虚拟存储器地址转换为实际存储器地址的最近使用的关联映射。该地图包括一堆存储设备，每个存储设备都有一个比较器。存储设备被布置在具有输入存储设备的下推堆叠中，以接收输入虚拟地址并存储相应的实际地址以及耦合到先前较高存储设备的输出的其他存储设备以及与存储设备最近使用存储最近最少使用的设备的最后或底部存储设备的顺序的虚拟地址和真实地址。当比较器检测到比较时，将实际地址提供出来，并且将转换作为最近使用的平移应用于输入存储设备，并且将其他平移向下移动以在与翻译进行比较的存储设备中替换从以前的存储设备。如果没有比较，则在输入存储设备输入新的翻译，而如果所有的存储设备都已满，则其他翻译被向下移动，最近最少使用的被翻转。

17. 发明授权

US4584574A Information display and editing system 失效
标题翻译：信息显示和编辑系统
公开(公告)号：US4584574A
公开(公告)日：1986-04-22
申请号：US532112
申请日：1983-09-14
申请人： William F. Beausoleil
发明人： William F. Beausoleil
IPC分类号： G09G1/08 , G09G1/16 , G09G1/26 , G09G1/00
CPC分类号： G09G1/16 , G09G1/08 , G09G1/26
摘要： A method and system is disclosed for displaying and editing information without flicker. Vector branch commands as well as the vectors comprising the information to be displayed are both divided into two groups. The first groups are those branch commands and vectors required to display the information requested in a recognizable form. The second groups are those branch commands and vectors required to completely display the information requested. Editing operations are performed on the recognizable form of the information to eliminate flicker. A REFRESH END COMMAND or a REFRESH END INCREMENT X COMMAND can also be used to delineate the two groups of branch commands. The REFRESH END INCREMENT X COMMAND also allows the user to add details to the display over and above those normally provided for editing operations. Faster raster-scan display refresh operations are also made possible by writing/reading only the points necessary to recognizably display images. A Character/Image End Table can also be used with the present invention to provide a separate storage area for move instructions. In addition, the advantages of the present invention can also be realized by fully displaying/refreshing only a limited portion of the screen at a time.
摘要翻译：公开了用于显示和编辑信息而不闪烁的方法和系统。向量分支命令以及包括要显示的信息的向量都被分成两组。第一组是以可识别形式显示所请求的信息所需的分支命令和向量。第二组是完全显示请求信息所需的分支命令和向量。以可识别的信息形式执行编辑操作以消除闪烁。 REFRESH END COMMAND或REFRESH END INCREMENT X COMMAND也可用于描绘两组分支命令。 REFRESH END INCREMENT X COMMAND还允许用户在显示屏上添加通常提供给编辑操作的信息。通过仅写入/读取可识别显示图像所需的点，也可以实现更快的光栅扫描显示刷新操作。字符/图像结束表也可以用于本发明以为移动指令提供单独的存储区域。此外，本发明的优点也可以通过一次完全显示/刷新屏幕的有限部分来实现。

18. 发明授权

US3987410A Array logic fabrication for use in pattern recognition equipments and the like 失效
标题翻译：用于图案识别设备等的阵列逻辑制造
公开(公告)号：US3987410A
公开(公告)日：1976-10-19
申请号：US482816
申请日：1974-06-24
申请人： William F. Beausoleil , Gerald H. Ottaway , Vaughn D. Winkler
发明人： William F. Beausoleil , Gerald H. Ottaway , Vaughn D. Winkler
IPC分类号： G06K9/46 , H03K19/177 , G06K9/06 , H03K19/08
CPC分类号： H03K19/17704 , G06K9/4609 , G06K2209/01
摘要： Improved features for a fabrication arrangement that reduces the number of LSI chips required in a bit stream measurement system comprised of a plurality of measurement elements, each element including a large programmable array. The improvements are on the basic fabrication arrangement of patent application Ser. No. 482,824. The improvements relate the chip and measurement element fabrication to the detection significance of parts of the bit stream by substituting delay shift registers for array portions to handle the less significant parts of the bit stream in some measurement elements. The detection operations can then be concentrated on the more significant parts of a bit stream, such as the part representing the top, bottom, left or right portion of an optical character recognition machines bit stream represented character frame. The resulting modifications in chip and element fabrication result in a further reduction in the average number of chips required in the measurement system. The LSI array chips can be identically made.
摘要翻译：改进了用于减少由多个测量元件组成的位流测量系统中所需的LSI芯片的数量的制造装置的特征，每个元件包括大的可编程阵列。改进在于专利申请Ser的基本制造安排。第482,824号。这些改进将芯片和测量元件制造与位流的部分的检测重要性相关联，通过代替阵列部分的延迟移位寄存器来处理某些测量元件中的比特流的较不重要的部分。然后，检测操作可以集中在比特流的更重要部分上，诸如表示表示字符帧的光学字符识别机比特流的顶部，底部，左部或右部分的部分。所产生的芯片和元件制造的改进导致测量系统中所需的平均芯片数量的进一步减少。 LSI阵列芯片可以相同地制作。

19. 发明授权

US08706469B2 Method and apparatus for increasing the efficiency of an emulation engine 有权
标题翻译：提高仿真引擎效率的方法和装置
公开(公告)号：US08706469B2
公开(公告)日：2014-04-22
申请号：US11344058
申请日：2006-01-31
申请人： William F. Beausoleil , Steven T. Comfort , Beshara G. Elmufdi
发明人： William F. Beausoleil , Steven T. Comfort , Beshara G. Elmufdi
IPC分类号： G06F9/455 , G06F17/50 , G06F13/10
CPC分类号： G06F17/5027 , G06F13/105 , G06F15/173 , G06F17/5054
摘要： A method and apparatus for improving the efficiency of a processor-based emulation engine. The emulation engine is composed of a plurality of processors, each processor capable of emulating a logic gate. Processors are arranged into groups of processors called clusters. Each processor receives inputs, processes the inputs, and stores the outputs in an output array. The output array allows processors within a cluster to fetch an output from a processor that was written to the output array during a previous cycle. The output array can also store and transfer data between clusters of processors. Consequently, the number of cycles that a processor or a cluster has to wait to fetch data is greatly reduced and the efficiency of the emulation engine is increased.
摘要翻译：一种用于提高基于处理器的仿真引擎的效率的方法和装置。仿真引擎由多个处理器组成，每个处理器能够仿真逻辑门。处理器被布置成称为簇的处理器组。每个处理器接收输入，处理输入，并将输出存储在输出阵列中。输出阵列允许集群内的处理器在上一个周期内从处理器获取输出到写入输出数组的输出。输出阵列还可以在处理器集群之间存储和传输数据。因此，处理器或集群必须等待获取数据的周期数大大减少，并且仿真引擎的效率增加。

20. 发明授权

US08160862B1 Method and apparatus for controlling power in an emulation system 有权
标题翻译：用于在仿真系统中控制功率的方法和装置
公开(公告)号：US08160862B1
公开(公告)日：2012-04-17
申请号：US11950797
申请日：2007-12-05
申请人： Mitchell Grant Poplack , William F. Beausoleil , N. James Tomassetti , Tung-sun Tung
发明人： Mitchell Grant Poplack , William F. Beausoleil , N. James Tomassetti , Tung-sun Tung
IPC分类号： G06F9/455 , G06G7/54
CPC分类号： G06F1/3287 , G06F1/3206 , G06F17/5027 , Y02D10/171
摘要： Method and apparatus for controlling power in an emulation system is described. In one example, power is controlled in a processor-based emulation system coupled to a host computer. A logic design is processed to identify unused resources in the emulation system during an emulation cycle. Power of the unused resources is controlled during emulation of a design under verification corresponding to the logic design by the emulation system. The resources may be identified as being unused during one or more steps of the emulation cycle. The power of the unused resources may be controlled by at least one of: powering down one or more of the unused resources; disabling one or more of the unused resources; freezing inputs to one or more of the unused resources; or setting inputs to one or more of the unused resources to a constant state. In this manner, power consumption of the emulation system is reduced.
摘要翻译：描述了用于在仿真系统中控制功率的方法和装置。在一个示例中，在耦合到主计算机的基于处理器的仿真系统中控制功率。在仿真周期期间，处理逻辑设计以识别仿真系统中的未使用资源。在模拟仿真期间控制未使用资源的功率，该设计在仿真系统对应于逻辑设计的验证下进行。可以在仿真周期的一个或多个步骤期间将资源识别为未被使用。未使用资源的功率可以由以下中的至少一个来控制：关闭一个或多个未使用的资源; 禁用一个或多个未使用的资源; 将输入冻结到一个或多个未使用的资源; 或将一个或多个未使用资源的输入设置为恒定状态。以这种方式，减少了仿真系统的功耗。

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