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1. 发明授权

US5551013A Multiprocessor for hardware emulation 失效
标题翻译：用于硬件仿真的多处理器
公开(公告)号：US5551013A
公开(公告)日：1996-08-27
申请号：US253881
申请日：1994-06-03
申请人： William F. Beausoleil , Tak-Kwong Ng , Harold R. Palmer
发明人： William F. Beausoleil , Tak-Kwong Ng , Harold R. Palmer
IPC分类号： G06F11/22 , G06F17/50 , G06F9/455
CPC分类号： G06F17/5027
摘要： A software-driven multiprocessor emulation system comprising a plurality of emulation processors connected in parallel in a module. One or more modules of processors comprise an emulation system. An execution unit in each processor includes a table-lookup unit for emulating any type of logic gate function. A parallel bus connects an output of each processor to a multiplexor input with every other processor in a module. Each processor embeds a control store to store software logic-representing signals for controlling operations of each processor. Also a data store is embedded in each processor to receive data generated under control of the software signals in the control store. The parallel processors on each module have a module input and a module output from each processor. The plurality of modules have their module outputs inter-connected to module inputs of all other modules. A sequencer synchronously cycles the processors through mini-cycles on all modules. Logic software drives all of the processors in the emulation system to emulate a complex array of Boolean logic, which may be all of the logic gates in a complex logic semiconductor chip. Special control means associated with the embedded control store and the embedded data store in each of the processors enables them to emulate all or part of a memory array within a target logic entity being emulated by the multiprocessor emulation system. Each cycle of processing may control the emulation of a level of logic being verified by the emulation processor.
摘要翻译：一种软件驱动的多处理器仿真系统，包括在模块中并联连接的多个仿真处理器。处理器的一个或多个模块包括仿真系统。每个处理器中的执行单元包括用于模拟任何类型的逻辑门功能的表查找单元。并行总线将每个处理器的输出与模块中的每个其他处理器连接到多路复用器输入。每个处理器嵌入控制存储器以存储用于控制每个处理器的操作的逻辑代表信号的软件。另外，在每个处理器中嵌入数据存储器以接收在控制存储器中的软件信号的控制下生成的数据。每个模块上的并行处理器具有模块输入和每个处理器的模块输出。多个模块的模块输出与所有其他模块的模块输入相互连接。定序器通过所有模块上的微循环同步循环处理器。逻辑软件驱动仿真系统中的所有处理器来仿真一个复杂的布尔逻辑阵列，它可能是复杂逻辑半导体芯片中的所有逻辑门。与嵌入式控制存储器相关联的特殊控制装置和每个处理器中的嵌入式数据存储器使得它们能够模拟由多处理器仿真系统仿真的目标逻辑实体内的存储器阵列的全部或部分。每个处理循环可以控制由仿真处理器验证的逻辑电平的仿真。

2. 发明授权

US6035117A Tightly coupled emulation processors 失效
标题翻译：紧耦合仿真处理器
公开(公告)号：US6035117A
公开(公告)日：2000-03-07
申请号：US52732
申请日：1998-03-31
申请人： William F. Beausoleil , Roy G. Musselman , Tak-Kwong Ng , Helmut Roth
发明人： William F. Beausoleil , Roy G. Musselman , Tak-Kwong Ng , Helmut Roth
IPC分类号： G06F15/16 , G06F11/22 , G06F17/50 , G06F9/455
CPC分类号： G06F17/5027
摘要： In an emulation system, the emulation processors are grouped in clusters which are capable of interchanging information between both input memory stacks and data memory stacks associated with each of the processor elements. This capability significantly enhances the performance of emulation engines and, in particular, it provides a mechanism for emulation of memory array elements in computer systems in a more efficient and faster manner.
摘要翻译：在仿真系统中，仿真处理器被分组成能够在输入存储器堆栈和与每个处理器元件相关联的数据存储器堆栈之间交换信息的簇。该功能显着提高了仿真引擎的性能，特别是提供了一种以更有效和更快速的方式在计算机系统中仿真存储器阵列元件的机制。

3. 发明授权

US5109496A Most recently used address translation system with least recently used (LRU) replacement 失效
标题翻译：最近使用的最近使用的地址转换系统（LRU）替换
公开(公告)号：US5109496A
公开(公告)日：1992-04-28
申请号：US413408
申请日：1989-09-27
申请人： William F. Beausoleil , Tak-Kwong Ng
发明人： William F. Beausoleil , Tak-Kwong Ng
IPC分类号： G06F12/10 , G06F12/12
CPC分类号： G06F12/123 , G06F12/1027
摘要： A least recently used associative map is described for translating virtual memory addresses to real memory addresses. The map includes a stack of storage devices each with a comparator. The storage devices are arranged in a push down stack with an input storage device to receive the incoming virtual address and store the corresponding real address and the other storage devices coupled to the output of the previous higher storage devices and with storage devices storing the translation of virtual address and real address in order of recent use with the last or bottom storage device storing the least recently used device. When the comparator detects a compare that real address is provided out and that translation is applied to the input storage device as the most recently used translation and the other translations are shifted down the stack to replace in the storage device that had the compare with the translation from the previous storage device. If there is not a compare a new translation is entered at the input storage device and the other translations are shifted down with the least recently used being shifted out if all the storage devices are full.
摘要翻译：描述了用于将虚拟存储器地址转换为实际存储器地址的最近使用的关联映射。该地图包括一堆存储设备，每个存储设备都有一个比较器。存储设备被布置在具有输入存储设备的下推堆叠中，以接收输入虚拟地址并存储相应的实际地址以及耦合到先前较高存储设备的输出的其他存储设备以及与存储设备最近使用存储最近最少使用的设备的最后或底部存储设备的顺序的虚拟地址和真实地址。当比较器检测到比较时，将实际地址提供出来，并且将转换作为最近使用的平移应用于输入存储设备，并且将其他平移向下移动以在与翻译进行比较的存储设备中替换从以前的存储设备。如果没有比较，则在输入存储设备输入新的翻译，而如果所有的存储设备都已满，则其他翻译被向下移动，最近最少使用的被翻转。

4. 发明授权

US6051030A Emulation module having planar array organization 失效
标题翻译：具有平面阵列组织的仿真模块
公开(公告)号：US6051030A
公开(公告)日：2000-04-18
申请号：US52417
申请日：1998-03-31
申请人： William F. Beausoleil , Tak-Kwong Ng
发明人： William F. Beausoleil , Tak-Kwong Ng
IPC分类号： H01L21/82 , G06F11/22 , G06F11/25 , G06F15/80 , G06F17/50 , G06F3/00
CPC分类号： G06F15/8023 , G06F17/5027
摘要： Emulation modules containing an increased number of emulation processors are logically reconfigured into a plurality of planes which are interconnected by means of multiplexors to avoid I/O pinout complexities introduced by the increase in the number of emulation processors. The emulation processors present on an emulation module chip or board are partitioned into a plurality N of different planes or arrays which are interconnected with one another and with off-chip or off-board components via N-way multiplexors. One set of multiplexors provides an input function for each of the planes. Another N-way multiplexor provides output functionality for these same set of planes. An output driver for off-board or chip communication is connected to an N-way output multiplexor. Likewise, an input receiver receives input from off-chip or off-board sources and supplies this signal to all of the N-way multiplexors which provide input signals to the various arrays of emulation processors. In this way, emulation engines are increased in capacity with virtually no impact on chip or module pinout connection problems.
摘要翻译：包含增加数量的仿真处理器的仿真模块在逻辑上被重新配置成多个平面，这些平面通过多路复用器互连，以避免由于仿真处理器数目的增加而引入的I / O引脚排列复杂性。存在于仿真模块芯片或板上的仿真处理器被分割成多个N个不同的平面或阵列，这些平面或阵列通过N路多路复用器彼此互连并且具有片外或片外组件。一组多路复用器为每个平面提供输入功能。另一个N路多路复用器为这些相同的平面组提供输出功能。用于板外或芯片通信的输出驱动器连接到N路输出多路复用器。类似地，输入接收器接收来自片外或离岸源的输入，并将该信号提供给向各种仿真处理器阵列提供输入信号的所有N路复用器。以这种方式，仿真引擎的容量增加，几乎不影响芯片或模块引脚分配连接问题。

5. 发明申请

US20070198892A1 Systems And Methods For Detecting A Failure Event In A Field Programmable Gate Array 有权
标题翻译：用于检测现场可编程门阵列中的故障事件的系统和方法
公开(公告)号：US20070198892A1
公开(公告)日：2007-08-23
申请号：US11531703
申请日：2006-09-14
申请人： Tak-Kwong Ng , Herath A. Jeffrey
发明人： Tak-Kwong Ng , Herath A. Jeffrey
IPC分类号： G11C29/00
CPC分类号： G11C29/08 , G01R31/318519 , G06F11/1008
摘要： An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.
摘要翻译：实施例一般涉及一种在现场可编程门阵列（FPGA）中自我检测错误的方法。该方法包括将签名值写入FPGA中的签名存储器中，并确定FPGA中配置刷新操作的结论。该方法还包括从签名存储器读取结果值。

6. 发明授权

US07590904B2 Systems and methods for detecting a failure event in a field programmable gate array 有权
标题翻译：用于检测现场可编程门阵列中的故障事件的系统和方法
公开(公告)号：US07590904B2
公开(公告)日：2009-09-15
申请号：US11531703
申请日：2006-09-14
申请人： Tak-Kwong Ng , Jeffrey A. Herath
发明人： Tak-Kwong Ng , Jeffrey A. Herath
IPC分类号： G01R31/28 , H03M13/00 , G06F11/00 , G06F7/38
CPC分类号： G11C29/08 , G01R31/318519 , G06F11/1008
摘要： An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.
摘要翻译：实施例一般涉及一种在现场可编程门阵列（FPGA）中自我检测错误的方法。该方法包括将签名值写入FPGA中的签名存储器中，并确定FPGA中配置刷新操作的结论。该方法还包括从签名存储器读取结果值。

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