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11. 发明申请

US20130145211A1 FLEXIBLE REPLICATION WITH SKEWED MAPPING IN MULTI-CORE CHIPS 审中-公开
标题翻译：灵活的复制与多核心卡片的映射映射
公开(公告)号：US20130145211A1
公开(公告)日：2013-06-06
申请号：US13460294
申请日：2012-04-30
申请人： Jian Li , William Evan Speight
发明人： Jian Li , William Evan Speight
IPC分类号： G06F11/20 , G06F12/08
CPC分类号： G06F1/1692
摘要： For a flexible replication with skewed mapping in a multi-core chip, a request for a cache line is received, at a receiver core in the multi-core chip from a requester core in the multi-core chip. The receiver and requester cores comprise electronic circuits. The multi-core chip comprises a set of cores including the receiver and the requester cores. A target core is identified from the request to which the request is targeted. A determination is made whether the target core includes the requester core in a neighborhood of the target core, the neighborhood including a first subset of cores mapped to the target core according to a skewed mapping. The cache line is replicated, responsive to the determining being negative, from the target core to a replication core. The cache line is provided from the replication core to the requester core.
摘要翻译：对于在多核芯片中具有偏斜映射的灵活复制，在多核芯片中的请求者核心的多核芯片的接收器核心处接收对高速缓存行的请求。接收机和请求者核心包括电子电路。多核芯片包括一组核心，包括接收机和请求者核心。从请求所针对的请求中识别目标核心。确定目标核心是否在目标核心的邻域中包括请求者核心，该邻域包括根据偏斜映射映射到目标核心的核心的第一子集。缓存行被复制，响应于确定为否定，从目标核心到复制核心。高速缓存行从复制核心提供给请求者核心。

12. 发明授权

US07698508B2 System and method for reducing unnecessary cache operations 失效
标题翻译：减少不必要的缓存操作的系统和方法
公开(公告)号：US07698508B2
公开(公告)日：2010-04-13
申请号：US11674960
申请日：2007-02-14
申请人： Ramakrishnan Rajamony , Hazim Shafi , William Evan Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , Hazim Shafi , William Evan Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0817
摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.
摘要翻译：一种用于数据处理系统中缓存管理的系统和方法。数据处理系统包括处理器和存储器层级。存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。

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