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11. 发明授权

US5619450A Drive circuit for flash memory with improved erasability 失效
标题翻译：闪存驱动电路，具有改进的可擦除性
公开(公告)号：US5619450A
公开(公告)日：1997-04-08
申请号：US440843
申请日：1995-05-15
申请人： Tetsuji Takeguchi
发明人： Tetsuji Takeguchi
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.
摘要翻译：本发明涉及擦除闪存的改进。本发明的目的是缩短擦除时间。在预擦除写入期间，一次以多行单位选择字线或位线中的至少一个，并且数据被同时写入多个选择晶体管。

12. 发明授权

US5592419A Flash memory with improved erasability and its circuitry 失效
公开(公告)号：US5592419A
公开(公告)日：1997-01-07
申请号：US441598
申请日：1995-05-15
申请人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
发明人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.

13. 发明授权

US5400276A Electrically erasable nonvolatile semiconductor memory that permits data readout despite the occurrence of over-erased memory cells 失效
标题翻译：电可擦除的非易失性半导体存储器，尽管存在过度擦除的存储器单元，但允许数据读出
公开(公告)号：US5400276A
公开(公告)日：1995-03-21
申请号：US181533
申请日：1994-01-14
申请人： Tetsuji Takeguchi
发明人： Tetsuji Takeguchi
IPC分类号： G11C16/04 , G11C16/08 , G11C16/16 , G11C11/24
CPC分类号： G11C16/08 , G11C16/0416 , G11C16/16
摘要： The purpose of the present invention is to provide an electrically erasable nonvolatile semiconductor memory that permits correct data readout despite the occurrence of over-erased memory cells. In the nonvolatile semiconductor memory of the invention, a select transistor whose gate is connected to a word line is provided for each group consisting of a plurality of memory cells, and the sources of the memory cells in the same group are connected to a common source via the select transistor. For writing and erasure, the source-drain relationship is reversed from that previously practiced, so that for writing the drain is grounded and a positive voltage is applied to the source while for erasure the source is grounded and a high voltage is applied to the drain. In a nonvolatile semiconductor memory according to another mode of the invention, a source line is provided independently for every one or a plurality of word lines. For reading, the source line, word line, and bit line to which the memory cell selected for reading is connected are supplied with a lower supply voltage, a higher supply voltage, and a positive voltage lower than the higher supply voltage, respectively, while the source lines and word lines to which the selected memory cell is not connected are supplied with the higher supply voltage and the lower supply voltage, respectively, and the bit lines to which the selected memory cell is not connected are opened.
摘要翻译：本发明的目的是提供一种电可擦除的非易失性半导体存储器，其允许正确的数据读出，尽管存在过度擦除的存储单元。在本发明的非易失性半导体存储器中，对于由多个存储单元组成的每个组提供栅极连接到字线的选择晶体管，并且同一组中的存储单元的源极连接到公共源通过选择晶体管。对于写入和擦除，源 - 漏关系与先前实践相反，使得写漏极接地并且正电压被施加到源，同时用于擦除源接地并且将高电压施加到漏极。在根据本发明的另一模式的非易失性半导体存储器中，对于每个或多个字线独立地提供源极线。对于读取，连接选择用于读取的存储单元的源极线，字线和位线分别被提供有较低电源电压，较高电源电压和低于较高电源电压的正电压，同时所选择的存储单元未连接到的源极线和字线分别被提供有更高的电源电压和较低的电源电压，并且打开所选存储单元未连接到的位线。

14. 发明申请

US20070053229A1 Redundancy substitution method, semiconductor memory device and information processing apparatus 有权
标题翻译：冗余替代方法，半导体存储装置和信息处理装置
公开(公告)号：US20070053229A1
公开(公告)日：2007-03-08
申请号：US11311485
申请日：2005-12-20
申请人： Osamu Iioka , Tetsuji Takeguchi , Hiroshi Mawatari
发明人： Osamu Iioka , Tetsuji Takeguchi , Hiroshi Mawatari
IPC分类号： G11C7/00
CPC分类号： G11C7/14 , G11C16/04 , G11C16/3418 , G11C29/50 , G11C29/50004
摘要： A redundancy substitution method for memory cells within an electrically writable and erasable semiconductor memory device, includes detecting a memory cell having a tendency of a charge loss and/or a charge gain, by use of a charge loss detecting reference cell and/or a charge gain detecting reference cell. The charge loss detecting reference cell has a threshold value set between a threshold value of a read reference cell and a threshold value of a write verify reference cell that is higher than that of the read reference cell, and the charge gain detecting reference cell has a threshold value set between the threshold value of the read reference cell and a threshold value of an erase verify reference cell that is lower than that of the read reference cell. The method subjects a memory cell whose tendency of the charge loss and/or the charge gain is detected to a redundancy substitution.
摘要翻译：一种用于电可写和可擦除半导体存储器件内的存储单元的冗余替换方法，包括通过使用电荷损失检测参考单元和/或电荷来检测具有电荷损失趋势和/或电荷增益的存储单元增益检测参考单元。电荷损失检测参考单元具有在读取参考单元的阈值和写入验证参考单元的阈值之间设置的阈值，该阈值高于读取的参考单元的阈值，并且电荷增益检测参考单元具有读取参考单元的阈值和擦除验证参考单元的阈值之间设置的阈值低于读取的参考单元的阈值。该方法对其中检测到电荷损失和/或电荷增益趋势的存储单元进行冗余替换。

15. 发明授权

US5608670A Flash memory with improved erasability and its circuitry 失效
标题翻译：闪存具有改进的可擦除性及其电路
公开(公告)号：US5608670A
公开(公告)日：1997-03-04
申请号：US436721
申请日：1995-05-08
申请人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
发明人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.
摘要翻译：本发明涉及擦除闪存的改进。本发明的目的是缩短擦除时间。在预擦除写入期间，一次以多行单位选择字线或位线中的至少一个，并且数据被同时写入多个选择晶体管。

16. 发明授权

US4720818A Semiconductor memory device adapted to carry out operation test 失效
标题翻译：半导体存储器件适于进行操作测试
公开(公告)号：US4720818A
公开(公告)日：1988-01-19
申请号：US875090
申请日：1986-06-17
申请人： Tetsuji Takeguchi
发明人： Tetsuji Takeguchi
IPC分类号： G11C17/00 , G11C8/12 , G11C16/08 , G11C29/00 , G11C29/02 , G11C29/12 , G11C29/34 , G11C29/50
CPC分类号： G11C29/025 , G11C16/08 , G11C29/02 , G11C29/34 , G11C29/50 , G11C8/12 , G11C16/04 , G11C2029/5004 , G11C2029/5006
摘要： In order to facilitate a test of the operations of a semiconductor memory device, the semiconductor memory device includes a line selection checking unit coupled to a cell matrix and column gates to form a logic gate circuit unit consisting of a plurality of transistors, the gates of the transistors being connected to word lines or bit lines. The line selection checking unit has a voltage or current detection portion connected to a pad for detecting an output voltage or current of the line selection checking unit.
摘要翻译：为了促进对半导体存储器件的操作的测试，半导体存储器件包括耦合到单元矩阵和列栅极的线选择检查单元，以形成由多个晶体管组成的逻辑门电路单元，栅极晶体管连接到字线或位线。线选择检查单元具有连接到焊盘的电压或电流检测部分，用于检测线选择检查单元的输出电压或电流。

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