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11. 发明申请

US20120319198A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120319198A1
公开(公告)日：2012-12-20
申请号：US13161503
申请日：2011-06-16
申请人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
发明人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/28158 , H01L21/28114 , H01L21/28185 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/49 , H01L29/4966 , H01L29/4983 , H01L29/51 , H01L29/517 , H01L29/66545
摘要： A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.
摘要翻译：提供了包括基板，间隔物和具有U形轮廓的高k电介质层的半导体器件。位于基板上的间隔件围绕并限定沟槽。具有U形轮廓的高k电介质层位于沟槽中，并且具有U形轮廓的高k电介质层露出沟槽的侧壁的上部。

12. 发明申请

US20120248507A1 METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：金属门结构及其制造方法
公开(公告)号：US20120248507A1
公开(公告)日：2012-10-04
申请号：US13072795
申请日：2011-03-28
申请人： Chih-Chien Liu , Chun-Yuan Wu , Chin-Fu Lin , Teng-Chun Tsai , Chin-Cheng Chien
发明人： Chih-Chien Liu , Chun-Yuan Wu , Chin-Fu Lin , Teng-Chun Tsai , Chin-Cheng Chien
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/517 , H01L21/28185 , H01L29/513 , H01L29/66545
摘要： A manufacturing method of a metal gate structure includes providing a substrate having at least a first metal oxide layer formed thereon, and transferring the surface of the first metal oxide layer into a second metal oxide layer. The first metal oxide layer includes a metal oxide (M1Ox) of a first metal (M1) and the second metal oxide layer includes a metal oxide ((M1M2Oy) of the first metal and a second metal (M2).
摘要翻译：金属栅极结构的制造方法包括提供具有形成在其上的至少第一金属氧化物层的基板，并将第一金属氧化物层的表面转移到第二金属氧化物层中。第一金属氧化物层包括第一金属（M1）的金属氧化物（M1Ox），第二金属氧化物层包括第一金属的金属氧化物（（M1M2Oy））和第二金属（M2）。

13. 发明申请

US20120220113A1 Method of Manufacturing Semiconductor Device Having Metal Gate 有权
标题翻译：具有金属栅极的半导体器件的制造方法
公开(公告)号：US20120220113A1
公开(公告)日：2012-08-30
申请号：US13033616
申请日：2011-02-24
申请人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Shui-Yen Lu , Pei-Yu Chou , Shin-Chi Chen , Jiunn-Hsiung Liao , Shang-Yuan Tsai , Chan-Lon Yang , Teng-Chun Tsai , Chun-Hsien Lin
发明人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Shui-Yen Lu , Pei-Yu Chou , Shin-Chi Chen , Jiunn-Hsiung Liao , Shang-Yuan Tsai , Chan-Lon Yang , Teng-Chun Tsai , Chun-Hsien Lin
IPC分类号： H01L21/28
CPC分类号： H01L29/66545 , H01L21/82345 , H01L21/823842 , H01L29/4966
摘要： The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.
摘要翻译：本发明提供一种制造具有金属栅极的半导体器件的方法。首先，提供基板。具有第一牺牲栅极的第一导电型晶体管和具有第二牺牲栅极的第二导电型晶体管设置在衬底上。去除第一牺牲栅极以形成第一沟槽，然后在第一沟槽中形成第一金属层和第一材料层。接下来，第一金属层和第一材料层变平。去除第二牺牲栅极以形成第二沟槽，然后在第二沟槽中形成第二金属层和第二材料层。最后，第二金属层和第二材料层变平。

14. 发明申请

US20120187563A1 PLANARIZATION METHOD APPLIED IN PROCESS OF MANUFACTURING SEMICONDUCTOR COMPONENT 有权
标题翻译：应用于制造半导体元件的方法的平面化方法
公开(公告)号：US20120187563A1
公开(公告)日：2012-07-26
申请号：US13012211
申请日：2011-01-24
申请人： Ya-Hsueh HSIEH , Teng-Chun Tsai , Wen-Chin Lin , Hsin-Kuo Hsu , Ren-Peng Huang , Chih-Hsien Chen , Chih-Chin Yang , Hung-Yuan Lu , Jen-Chieh Lin , Wei-Che Tsao
发明人： Ya-Hsueh HSIEH , Teng-Chun Tsai , Wen-Chin Lin , Hsin-Kuo Hsu , Ren-Peng Huang , Chih-Hsien Chen , Chih-Chin Yang , Hung-Yuan Lu , Jen-Chieh Lin , Wei-Che Tsao
IPC分类号： H01L23/532 , H01L21/28
CPC分类号： H01L21/7684 , H01L21/3212 , H01L29/4966 , H01L29/517
摘要： A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.
摘要翻译：提供了制造半导体部件的平面化方法。介电层形成在衬底之上并在其中限定沟槽。在沟槽中依次形成阻挡层和金属层。通过使用第一反应物将第一平面化工艺施加到金属层，使得金属层的一部分被去除。第一反应物对金属层的蚀刻速率大于第一反应物对阻挡层的蚀刻速率。通过使用第二反应物将阻挡层和金属层施加第二平坦化工艺，使得去除阻挡层和金属层的一部分以暴露电介质层。第二反应物对阻挡层的蚀刻速率大于第二反应物对金属层的蚀刻速率。

15. 发明申请

US20110169095A1 STRAINED-SILICON TRANSISTOR AND METHOD OF MAKING THE SAME 有权
标题翻译：应变硅晶体管及其制造方法
公开(公告)号：US20110169095A1
公开(公告)日：2011-07-14
申请号：US12687133
申请日：2010-01-14
申请人： Jei-Ming Chen , Hsiu-Lien Liao , Yu-Tuan Tsai , Teng-Chun Tsai
发明人： Jei-Ming Chen , Hsiu-Lien Liao , Yu-Tuan Tsai , Teng-Chun Tsai
IPC分类号： H01L27/092 , H01L21/3205
CPC分类号： H01L21/823807 , H01L21/76832 , H01L21/76834 , H01L29/7843
摘要： A structure of a strained-silicon transistor includes a PMOS disposed on a substrate, a silicon nitride layer positioned on the PMOS, and a compressive stress film disposed on the silicon nitride layer, wherein the silicon nitride has a stress between −0.1 Gpa and −3.2 Gpa, and the stress of the silicon nitride is smaller than the stress of the compressive stress layer.
摘要翻译：应变硅晶体管的结构包括设置在衬底上的PMOS，位于PMOS上的氮化硅层和设置在氮化硅层上的压应力膜，其中氮化硅的应力为-0.1Gpa至 - 3.2 Gpa，氮化硅的应力小于压应力层的应力。

16. 发明授权

US07645712B2 Method of forming contact 有权
标题翻译：形成接触的方法
公开(公告)号：US07645712B2
公开(公告)日：2010-01-12
申请号：US12345670
申请日：2008-12-30
申请人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang
发明人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang
IPC分类号： H01L21/469 , H01L21/338
CPC分类号： H01L21/76801 , H01L21/76837 , H01L29/78
摘要： A substrate having at least two metal oxide semiconductor devices of a same conductive type and a gap formed between the two devices is provided. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate, filling the gap. An etching back process is then performed to remove a portion of the stress material layer inside the gap. A second stress layer and a dielectric layer are sequentially formed on the first stress layer. The first stress layer and the second stress layer provide a same type of stress. A portion of the second stress layer is removed to form a contact opening. A second conductive layer is filled into the contact opening to form a contact.
摘要翻译：提供了具有至少两个相同导电类型的金属氧化物半导体器件和在两个器件之间形成的间隙的衬底。第一应力层形成在衬底上以覆盖金属氧化物半导体器件和衬底，填补间隙。然后执行回蚀处理以去除间隙内部的应力材料层的一部分。第一应力层和电介质层依次形成在第一应力层上。第一应力层和第二应力层提供相同类型的应力。去除第二应力层的一部分以形成接触开口。将第二导电层填充到接触开口中以形成接触。

17. 发明授权

US07544305B2 Chemical mechanical polishing process for forming shallow trench isolation structure 有权
标题翻译：用于形成浅沟槽隔离结构的化学机械抛光工艺
公开(公告)号：US07544305B2
公开(公告)日：2009-06-09
申请号：US11863665
申请日：2007-09-28
申请人： Chia-Jung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
发明人： Chia-Jung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
IPC分类号： B44C1/22
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.
摘要翻译：提供了一种用于形成浅沟槽隔离结构的浅沟槽隔离（STI）多级化学机械抛光（CMP）方法。所述基板包括致密区域和隔离区域，在所述基板上形成的氮化硅层，形成在所述氮化硅层和所述基板中的多个沟槽，形成在所述基板上方的填充所述沟槽的氧化物层，密集区域中的沟槽小于隔离区域中的沟槽。执行第一抛光步骤以除去氧化硅层的一部分直到氧化物层的剩余部分的厚度达到预定厚度。执行第二抛光步骤以去除氧化硅层的剩余部分的一部分，直到暴露氮化硅层。

18. 发明申请

US20080166888A1 STI OF A SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：一种半导体器件的STI及其制造方法
公开(公告)号：US20080166888A1
公开(公告)日：2008-07-10
申请号：US11621968
申请日：2007-01-10
申请人： Shao-Ta Hsu , Neng-Kuo Chen , Teng-Chun Tsai
发明人： Shao-Ta Hsu , Neng-Kuo Chen , Teng-Chun Tsai
IPC分类号： H01L21/31
CPC分类号： H01L21/31612 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02337 , H01L21/76224
摘要： A method for filling silicon nitride materials into a trench includes providing a substrate having a plurality of trenches, performing a first deposition process to form a first silicon nitride layer in the trenches, and performing a second deposition process to form a second silicon nitride layer in the trenches. The reactant gas of the first deposition process has a first O3/TEOS flow ratio larger than a second O3/TEOS flow ratio of the reactant gas of the second deposition process.
摘要翻译：将氮化硅材料填充到沟槽中的方法包括提供具有多个沟槽的衬底，执行第一沉积工艺以在沟槽中形成第一氮化硅层，以及执行第二沉积工艺以形成第二氮化硅层壕沟第一沉积工艺的反应气体具有大于第二沉积工艺的反应气体的第二O 3 / TEOS流动比的第一O 3 / TEOS流动比。

19. 发明申请

US20080142902A1 METHOD FOR FABRICATING ULTRA-HIGH TENSILE-STRESSED FILM AND STRAINED-SILICON TRANSISTORS THEREOF 有权
标题翻译：制造超高压应力薄膜及其应变硅晶体管的方法
公开(公告)号：US20080142902A1
公开(公告)日：2008-06-19
申请号：US12013482
申请日：2008-01-14
申请人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang , Tsai-Fu Chen , Wen-Han Hung
发明人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang , Tsai-Fu Chen , Wen-Han Hung
IPC分类号： H01L29/78
CPC分类号： H01L21/0217 , C23C16/345 , C23C16/56 , H01L21/02274 , H01L21/02348 , H01L21/3185 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A metal-oxide-semiconductor (MOS) transistor device is disclosed. The MOS transistor device comprises a semiconductor substrate; a gate structure on the semiconductor substrate; source/drain regions on the semiconductor substrate adjacent to the gate structure; an ultra-high tensile-stressed nitride film having a hydrogen concentration of less than 1E22 atoms/cm3 covering the gate structure and the source/drain regions; and an inter-layer dielectric (ILD) film over the ultra-high tensile-stressed nitride film.
摘要翻译：公开了一种金属氧化物半导体（MOS）晶体管器件。 MOS晶体管器件包括半导体衬底; 半导体衬底上的栅极结构; 与栅极结构相邻的半导体衬底上的源/漏区; 具有覆盖栅极结构和源极/漏极区域的小于1E22原子/ cm 3的氢浓度的超高拉伸应力氮化物膜; 和超高拉伸应力氮化物膜上的层间电介质（ILD）膜。

20. 发明申请

US20080099801A1 METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND METHOD OF FORMING THE SAME 有权
标题翻译：金属氧化物半导体晶体管及其形成方法
公开(公告)号：US20080099801A1
公开(公告)日：2008-05-01
申请号：US11552532
申请日：2006-10-25
申请人： Kun-Hsien Lee , Cheng-Tung Huang , Wen-Han Hung , Shyh-Fann Ting , Li-Shian Jeng , Tzyy-Ming Cheng , Neng-Kuo Chen , Shao-Ta Hsu , Teng-Chun Tsai , Chien-Chung Huang
发明人： Kun-Hsien Lee , Cheng-Tung Huang , Wen-Han Hung , Shyh-Fann Ting , Li-Shian Jeng , Tzyy-Ming Cheng , Neng-Kuo Chen , Shao-Ta Hsu , Teng-Chun Tsai , Chien-Chung Huang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00 , H01L21/8234 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823835 , H01L21/82385 , H01L21/823864 , H01L29/6653 , H01L29/6656 , H01L29/7843
摘要： A method of manufacturing a MOS transistor device. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.
摘要翻译：一种制造MOS晶体管器件的方法。首先，准备具有栅极结构的半导体衬底。栅极结构在侧壁上具有两个侧壁和衬垫。随后，在半导体衬底上形成应力覆盖层，并覆盖栅极结构和衬垫。接下来，执行激活处理。此外，将应力覆盖层蚀刻成为自对准硅化物块。之后，进行自对准处理以在未被应力覆盖层覆盖的区域上形成硅化物层。

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