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11. 发明授权

US09194036B2 Plasma vapor deposition 有权
标题翻译：等离子体气相沉积
公开(公告)号：US09194036B2
公开(公告)日：2015-11-24
申请号：US11851269
申请日：2007-09-06
申请人： Sun-Oo Kim , Moosung Chae , Bum Ki Moon
发明人： Sun-Oo Kim , Moosung Chae , Bum Ki Moon
IPC分类号： C23C14/34 , H01J37/34
CPC分类号： C23C14/3464 , C23C14/3407 , C23C14/3471 , H01J37/34 , H01J37/3414 , H01J37/3417 , H01J37/3423
摘要： A plasma vapor deposition system is described for forming a feature on a semiconductor wafer. The plasma vapor deposition comprises a primary target electrode and a plurality of secondary target electrodes. The deposition is performed by sputtering atoms off the primary and secondary target electrodes.
摘要翻译：描述了用于在半导体晶片上形成特征的等离子体气相沉积系统。等离子体气相沉积包括主要目标电极和多个次要目标电极。通过从初级和次级目标电极溅射原子来进行沉积。

12. 发明申请

US20120282753A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120282753A1
公开(公告)日：2012-11-08
申请号：US13100770
申请日：2011-05-04
申请人： Sun-Oo Kim
发明人： Sun-Oo Kim
IPC分类号： H01L21/3205
CPC分类号： H01L28/82 , H01L23/5223 , H01L28/86 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： Capacitor plates, capacitors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes at least one via and at least one conductive member coupled to the at least one via. The at least one conductive member comprises an enlarged region proximate the at least one via.
摘要翻译：公开了电容器板，电容器，半导体器件及其制造方法。在一个实施例中，电容器板包括耦合到至少一个通孔的至少一个通孔和至少一个导电构件。所述至少一个导电构件包括靠近所述至少一个通孔的放大区域。

13. 发明授权

US07626268B2 Support structures for semiconductor devices 有权
标题翻译：半导体器件的支撑结构
公开(公告)号：US07626268B2
公开(公告)日：2009-12-01
申请号：US11248554
申请日：2005-10-12
申请人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
发明人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
IPC分类号： H01L21/4763
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05556 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/45015 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/20754 , H01L2924/30105 , H01L2924/00 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20755 , H01L2224/05599
摘要： Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The central region inside the substantially annular shape of the plurality of support members may be used to route functional conductive lines for making electrical contact to active areas of the semiconductor device. Dummy support structures may optionally be formed between the functional conductive lines. The support structures may be formed in one or more conductive line layers and semiconductive material layers of a semiconductor device. In other embodiments, support members are not formed in an annular shape, and are formed in insulating layers that do not comprise low dielectric constant (k) materials.
摘要翻译：公开了半导体器件的支撑结构及其制造方法。在一些实施例中，支撑结构包括在线接合区域下方形成为大致环形的多个支撑构件。多个支撑构件的大致环形形状内的中心区域可以用于路由功能导电线，用于与半导体器件的有源区电接触。可选地，在功能导电线之间形成虚拟支撑结构。支撑结构可以形成在半导体器件的一个或多个导电层和半导体材料层中。在其它实施例中，支撑构件不形成为环形，并且形成为不包括低介电常数（k）材料的绝缘层。

14. 发明申请

US20090243036A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090243036A1
公开(公告)日：2009-10-01
申请号：US12059457
申请日：2008-03-31
申请人： Sun-Oo Kim
发明人： Sun-Oo Kim
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L23/5223 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Capacitor plates, capacitors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes at least one via and at least one conductive member coupled to the at least one via. The at least one conductive member comprises an enlarged region proximate the at least one via.
摘要翻译：公开了电容器板，电容器，半导体器件及其制造方法。在一个实施例中，电容器板包括耦合到至少一个通孔的至少一个通孔和至少一个导电构件。所述至少一个导电构件包括靠近所述至少一个通孔的放大区域。

15. 发明申请

US20090065349A1 Plasma Vapor Deposition 有权
标题翻译：等离子体气相沉积
公开(公告)号：US20090065349A1
公开(公告)日：2009-03-12
申请号：US11851269
申请日：2007-09-06
申请人： Sun-Oo Kim , Moosung Chae , Bum Ki Moon
发明人： Sun-Oo Kim , Moosung Chae , Bum Ki Moon
IPC分类号： C23C14/00
CPC分类号： C23C14/3464 , C23C14/3407 , C23C14/3471 , H01J37/34 , H01J37/3414 , H01J37/3417 , H01J37/3423
摘要： A plasma vapor deposition system is described for forming a feature on a semiconductor wafer. The plasma vapor deposition comprises a primary target electrode and a plurality of secondary target electrodes. The deposition is performed by sputtering atoms off the primary and secondary target electrodes.
摘要翻译：描述了用于在半导体晶片上形成特征的等离子体气相沉积系统。等离子体气相沉积包括主要目标电极和多个次要目标电极。通过从初级和次级目标电极溅射原子来进行沉积。

16. 发明申请

US20090057923A1 Methods of Fabricating Semiconductor Devices and Structures Thereof 有权
标题翻译：制造半导体器件及其结构的方法
公开(公告)号：US20090057923A1
公开(公告)日：2009-03-05
申请号：US11849535
申请日：2007-09-04
申请人： Sun-Oo Kim , Yoon-Hae Kim
发明人： Sun-Oo Kim , Yoon-Hae Kim
IPC分类号： H01L23/52 , H01L21/311 , H01L21/4763
CPC分类号： H01L23/522 , H01L21/76801 , H01L21/7682 , H01L21/76835 , H01L21/7684 , H01L23/5222 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a first insulating material over the semiconductor wafer, and forming a plurality of first features and a plurality of second features in the first insulating material. The plurality of first features is removed, leaving an unfilled pattern in the first insulating material. The unfilled pattern in the first insulating material is filled with a second insulating material.
摘要翻译：公开了制造半导体器件的方法及其结构。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片上形成第一绝缘材料，以及在第一绝缘材料中形成多个第一特征和多个第二特征。去除多个第一特征，在第一绝缘材料中留下未填充图案。第一绝缘材料中的未填充图案填充有第二绝缘材料。

17. 发明申请

US20080173538A1 Method and apparatus for sputtering 审中-公开
标题翻译：溅射的方法和装置
公开(公告)号：US20080173538A1
公开(公告)日：2008-07-24
申请号：US11655488
申请日：2007-01-19
申请人： Sun-Oo Kim , Bum Ki Moon , Erdom Kaltalioglu
发明人： Sun-Oo Kim , Bum Ki Moon , Erdom Kaltalioglu
IPC分类号： C23C14/34
CPC分类号： H01J37/34 , H01J37/32082 , H01J37/32706
摘要： A sputtering apparatus includes a target electrode and a bias source electrically coupled to the target electrode. A wafer chuck is spaced from the target electrode. The wafer chuck is partitioned into a plurality of zones, each zone being coupled to receive an AC signal having an amplitude that can vary by zone. At least one RF coil is positioned adjacent a space between the target electrode and the wafer chuck.
摘要翻译：溅射装置包括目标电极和与靶电极电耦合的偏压源。晶片卡盘与目标电极间隔开。晶片卡盘被划分成多个区域，每个区域被耦合以接收具有可以随区域变化的幅度的AC信号。至少一个RF线圈被定位成邻近目标电极和晶片卡盘之间的空间。

18. 发明申请

US20060105557A1 Method of making fully silicided gate electrode 有权
标题翻译：制作完全硅化栅电极的方法
公开(公告)号：US20060105557A1
公开(公告)日：2006-05-18
申请号：US10988113
申请日：2004-11-12
申请人： Veit Klee , Sun-Oo Kim
发明人： Veit Klee , Sun-Oo Kim
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L29/6653 , H01L21/28097 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： A method of making a semiconductor device for an integrated circuit chip. An interim gate electrode stack formed includes a top silicon portion patterned from a second silicon layer, a sandwiched oxide portion patterned from an etch stop oxide layer, and a bottom silicon portion patterned from a first silicon layer formed on a gate dielectric layer over a substrate. Etching the second silicon layer is stopped at the etch stop oxide layer. A spacer structure is formed about the interim gate electrode stack, and then the top silicon portion and the sandwiched oxide portion are removed. The spacer structure height may be reduced. A metal layer is formed over the bottom silicon portion of the interim gate electrode stack and over source and drain regions of the substrate, all of which are silicided at the same time to form a fully silicided (FUSI) gate electrode and silicided source and drain regions.
摘要翻译：制造用于集成电路芯片的半导体器件的方法。形成的中间栅极电极堆叠包括从第二硅层图案化的顶部硅部分，从蚀刻停止氧化物层图案化的夹层氧化物部分和从在衬底上形成的栅极电介质层上形成的第一硅层图案化的底部硅部分。蚀刻第二硅层在蚀刻停止氧化物层处停止。围绕临时栅电极堆叠形成间隔结构，然后去除顶部硅部分和夹层氧化物部分。可以减小间隔件结构的高度。在中间栅极电极堆叠的底部硅部分上方和衬底的源极和漏极区域之上形成金属层，所有这些都被同时硅化以形成完全硅化（FUSI）栅极电极和硅化物源极和漏极地区。

19. 发明申请

US20050112836A1 MIM capacitor structure and method of fabrication 有权
标题翻译： MIM电容器结构及其制造方法
公开(公告)号：US20050112836A1
公开(公告)日：2005-05-26
申请号：US10720450
申请日：2003-11-24
申请人： Sun-Oo Kim , Ernst Demm
发明人： Sun-Oo Kim , Ernst Demm
IPC分类号： H01L21/02 , H01L23/522 , H01L21/20 , H01L21/336 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/60 , H01L23/5223 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal-insulator-metal (MIM) capacitor wherein a plate of a MIM capacitor is formed in the entire thickness of a metallization layer of a semiconductor device. At least one thin conductive material layer is disposed within the material of the metallization layer to reduce the surface roughness of the metallization layer, thus improving the reliability of the MIM capacitor. The thin conductive material layer may comprise TiN, TaN, or WN and may alternatively comprise a barrier layer disposed over or under the TiN, TaN, or WN. One plate of the MIM capacitor is patterned using the same mask that is used to pattern conductive lines in a metallization layer, thus reducing the number of masks that are required to manufacture the MIM capacitor.
摘要翻译：一种形成金属绝缘体金属（MIM）电容器的方法，其中在半导体器件的金属化层的整个厚度上形成MIM电容器的板。至少一个薄导电材料层设置在金属化层的材料内，以减小金属化层的表面粗糙度，从而提高MIM电容器的可靠性。薄导电材料层可以包括TiN，TaN或WN，并且还可以包括设置在TiN，TaN或WN之上或之下的阻挡层。使用与用于在金属化层中形成导线的掩模相同的掩模对MIM电容器的一个板进行构图，从而减少制造MIM电容器所需的掩模的数量。

20. 发明授权

US08197660B2 Electro chemical deposition systems and methods of manufacturing using the same 有权
标题翻译：电化学沉积系统及使用其的制造方法
公开(公告)号：US08197660B2
公开(公告)日：2012-06-12
申请号：US11852910
申请日：2007-09-10
申请人： Moosung Chae , Bum Ki Moon , Sun-Oo Kim , Danny Pak-Chum Shum
发明人： Moosung Chae , Bum Ki Moon , Sun-Oo Kim , Danny Pak-Chum Shum
IPC分类号： C25D5/00
CPC分类号： H01L21/76877 , C25D5/02 , C25D17/001 , C25D17/007 , C25D17/12 , C25D21/12 , H01L21/2885
摘要： An electro chemical deposition system is described for forming a feature on a semiconductor wafer. The electro chemical deposition is performed by powering electrodes that includes a cathode, an anode and a plurality of electrically independent auxiliary electrodes.
摘要翻译：描述了用于在半导体晶片上形成特征的电化学沉积系统。电化学沉积通过为包括阴极，阳极和多个电独立辅助电极的电极供电来执行。

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