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11. 发明授权

US07687859B2 Electronic circuit and method of manufacturing an electronic circuit 有权
标题翻译：电子电路及其制造方法
公开(公告)号：US07687859B2
公开(公告)日：2010-03-30
申请号：US11852068
申请日：2007-09-07
申请人： Christian Russ , David Trémouilles , Steven Thijs
发明人： Christian Russ , David Trémouilles , Steven Thijs
IPC分类号： H01L23/62
CPC分类号： H01L27/12 , H01L21/845 , H01L27/0248 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/66803 , H01L29/785
摘要： An electronic circuit includes at least one field effect transistor that is to be protected against electrostatic discharge events, and at least one protection field effect transistor. The protection field effect transistor has a crystal orientation that is different from a crystal orientation of the field effect transistor to be protected.
摘要翻译：电子电路包括至少一个待被保护以防止静电放电事件的场效应晶体管，以及至少一个保护场效应晶体管。保护场效应晶体管具有与待保护的场效应晶体管的晶体取向不同的晶体取向。

12. 发明申请

US20090280582A1 Design Methodology for MuGFET ESD Protection Devices 有权
标题翻译： MuGFET ESD保护器件的设计方法
公开(公告)号：US20090280582A1
公开(公告)日：2009-11-12
申请号：US12437294
申请日：2009-05-07
申请人： Steven Thijs , Dimitri Linten , David Eric Tremouilles
发明人： Steven Thijs , Dimitri Linten , David Eric Tremouilles
IPC分类号： H01L21/66
CPC分类号： H01L27/0248 , H01L29/66795
摘要： A method for manufacturing a MuGFET ESD protection device having a given layout by means of a given manufacturing process, the method comprising selecting multiple interdependent layout and process parameters of which a first set are fixed by said manufacturing process and a second set are variable, selecting multiple combinations of possible layout and process parameter values which meet predetermined ESD constraints; determining an optimum value for at least one other parameter in view of a predetermined design target apart from the predetermined ESD constraints; determining values for fin width (Wfin), gate length (LG) and number of fins (N) on the basis of the optimum value; and manufacturing said MuGFET ESD protection device using the given manufacturing and process values.
摘要翻译：一种通过给定的制造工艺制造具有给定布局的MuGFET ESD保护装置的方法，所述方法包括：通过所述制造过程选择第一组固定的多个相互依赖的布局和工艺参数，第二组是可变的，选择可能的布局和过程参数值的多种组合满足预定的ESD约束; 鉴于除了预定的ESD约束之外的预定设计目标，确定至少一个其他参数的最佳值; 基于最佳值确定翅片宽度（Wfin），栅极长度（LG）和翅片数（N）的值; 并使用给定的制造和过程值制造所述MuGFET ESD保护装置。

13. 发明申请

US20090065868A1 Electronic Circuit and Method of Manufacturing an Electronic Circuit 有权
标题翻译：电子电路和电子电路制造方法
公开(公告)号：US20090065868A1
公开(公告)日：2009-03-12
申请号：US11852068
申请日：2007-09-07
申请人： Christian Russ , David Tremouilles , Steven Thijs
发明人： Christian Russ , David Tremouilles , Steven Thijs
IPC分类号： H01L27/12 , H01L21/8238 , H01L29/94
CPC分类号： H01L27/12 , H01L21/845 , H01L27/0248 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/66803 , H01L29/785
摘要： An electronic circuit includes at least one field effect transistor that is to be protected against electrostatic discharge events, and at least one protection field effect transistor. The protection field effect transistor has a crystal orientation that is different from a crystal orientation of the field effect transistor to be protected.
摘要翻译：电子电路包括至少一个待被保护以防止静电放电事件的场效应晶体管，以及至少一个保护场效应晶体管。保护场效应晶体管具有与待保护的场效应晶体管的晶体取向不同的晶体取向。

14. 发明申请

US20070247772A1 ESD CLAMP CONTROL BY DETECTION OF POWER STATE 审中-公开
标题翻译：通过检测电源状态的ESD钳位控制
公开(公告)号：US20070247772A1
公开(公告)日：2007-10-25
申请号：US11737469
申请日：2007-04-19
申请人： Bart Keppens , Benjamin Van Camp , Aagje Bens , Pieter Vanysacker , Steven Thijs
发明人： Bart Keppens , Benjamin Van Camp , Aagje Bens , Pieter Vanysacker , Steven Thijs
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： The present invention provides an improvement on ESD protection circuitry by controlling the trigger circuit to prevent the unwanted triggering of the device. The circuitry includes an ESD clamp with a trigger circuit coupled to the clamp. Both the clamp and the trigger circuit are coupled to a first reference potential. The circuitry also includes a control line coupled to the trigger circuit. The control line is coupled to a second reference potential to further control the behavior of the trigger circuit such that when the power is supplied to the second reference potential, the control line disables the trigger circuit, and when power is not supplied to the second reference potential, the control line enables the trigger circuit.
摘要翻译：本发明通过控制触发电路来防止不期望的触发装置来提供ESD保护电路的改进。该电路包括具有与钳位件耦合的触发电路的ESD钳位。钳位电路和触发电路都耦合到第一参考电位。电路还包括耦合到触发电路的控制线。控制线耦合到第二参考电位以进一步控制触发电路的行为，使得当电力被提供给第二参考电位时，控制线禁止触发电路，并且当不向第二参考电源供电时电位，控制线使能触发电路。

15. 发明申请

US20070058308A1 Electrostatic discharge protected circuits 有权
标题翻译：静电放电保护电路
公开(公告)号：US20070058308A1
公开(公告)日：2007-03-15
申请号：US11521293
申请日：2006-09-14
申请人： Steven Thijs , Natarajan Mahadeva Iyer , Dimitri Linten
发明人： Steven Thijs , Natarajan Mahadeva Iyer , Dimitri Linten
IPC分类号： H02H9/00
CPC分类号： H03F1/223 , H01L27/0251 , H03F1/52 , H03F1/523 , H03F3/191 , H03F3/195 , H03F3/605 , H03F2200/294 , H03F2200/451 , H03F2200/489
摘要： A method for designing an ESD protected analog circuit is described. The method includes creating an analog circuit design comprising a plurality of interconnected functional components and circuit-level ESD protection components with predetermined electric properties for achieving a predetermined analog performance during normal operation of the circuit as well as a predetermined ESD robustness during an ESD event on the circuit. At least one ESD event is simulated on the analog circuit design to identify at least one weak spot in the circuit. Component-level ESD protection components are added into the analog circuit design around each identified weak spot to reduce failure of the weak spot during an ESD event.
摘要翻译：描述了一种用于设计ESD保护的模拟电路的方法。该方法包括创建模拟电路设计，其包括具有预定电特性的多个互连功能部件和电路级ESD保护部件的模拟电路设计，以在电路的正常操作期间实现预定的模拟性能以及在ESD事件期间预定的ESD稳健性电路。在模拟电路设计中模拟至少一个ESD事件，以识别电路中的至少一个弱点。组件级ESD保护组件被添加到围绕每个识别的弱点的模拟电路设计中，以减少ESD事件期间弱点的故障。

16. 发明授权

US07923266B2 Design methodology for MuGFET ESD protection devices 有权
标题翻译： MuGFET ESD保护装置的设计方法
公开(公告)号：US07923266B2
公开(公告)日：2011-04-12
申请号：US12437294
申请日：2009-05-07
申请人： Steven Thijs , Dimitri Linten , David Eric Trémouilles
发明人： Steven Thijs , Dimitri Linten , David Eric Trémouilles
IPC分类号： H01L21/66 , H01L21/332 , H01L21/00 , H01L21/84 , H01L21/336
CPC分类号： H01L27/0248 , H01L29/66795
摘要： A method for manufacturing a MuGFET ESD protection device having a given layout by means of a given manufacturing process, the method comprising selecting multiple interdependent layout and process parameters of which a first set are fixed by said manufacturing process and a second set are variable, selecting multiple combinations of possible layout and process parameter values which meet predetermined ESD constraints; determining an optimum value for at least one other parameter in view of a predetermined design target apart from the predetermined ESD constraints; determining values for fin width (Wfin), gate length (LG) and number of fins (N) on the basis of the optimum value; and manufacturing said MuGFET ESD protection device using the given manufacturing and process values.
摘要翻译：一种通过给定的制造工艺制造具有给定布局的MuGFET ESD保护装置的方法，所述方法包括：通过所述制造过程选择第一组固定的多个相互依赖的布局和工艺参数，第二组是可变的，选择可能的布局和过程参数值的多种组合满足预定的ESD约束; 鉴于除了预定的ESD约束之外的预定设计目标，确定至少一个其他参数的最佳值; 基于最佳值确定翅片宽度（Wfin），栅极长度（LG）和翅片数（N）的值; 并使用给定的制造和过程值制造所述MuGFET ESD保护装置。

17. 发明申请

US20100142105A1 Bidirectional ESD Power Clamp 审中-公开
标题翻译：双向ESD电源钳位
公开(公告)号：US20100142105A1
公开(公告)日：2010-06-10
申请号：US12630170
申请日：2009-12-03
申请人： Dimitri Linten , Steven Thijs , David Eric Tremouilles , Natarajan Mahadeva Iyer
发明人： Dimitri Linten , Steven Thijs , David Eric Tremouilles , Natarajan Mahadeva Iyer
IPC分类号： H02H9/04
CPC分类号： H01L27/0285
摘要： The disclosed method and device relates to a bidirectional ESD power clamp, comprising a semiconductor structure (BigNFET; BigPFET) having a conductive path connected between first and second nodes and having a triggering node via which the conductive path can be triggered. An ESD transient detection circuit is connected between the first and second nodes and to the triggering node and comprises a first part for detecting an occurrence of a first ESD transient on the first node. The semiconductor structure is provided on an insulator substrate, such that a parasitic conductive path between said first and second nodes via the substrate is avoided. The ESD transient detection circuit further comprises a second part for detecting an occurrence of a second ESD transient on the second node.
摘要翻译：所公开的方法和装置涉及双向ESD功率钳位，其包括半导体结构（BigNFET; BigPFET），其具有连接在第一和第二节点之间的导电路径，并且具有触发节点，通过该触发节点可以触发导电路径。 ESD瞬变检测电路连接在第一和第二节点与触发节点之间，并且包括用于检测第一节点上的第一ESD瞬变的发生的第一部分。半导体结构设置在绝缘体基板上，使得避免了经由基板的所述第一和第二节点之间的寄生导电路径。 ESD瞬态检测电路还包括用于检测第二节点上的第二ESD瞬态的发生的第二部分。

18. 发明申请

US20090027063A1 Method for Calibrating an Electrostatic Discharge Tester 有权
标题翻译：校准静电放电测试仪的方法
公开(公告)号：US20090027063A1
公开(公告)日：2009-01-29
申请号：US12051749
申请日：2008-03-19
申请人： Mirko Scholz , David Eric Tremouilles , Steven Thijs , Dimitri Linten
发明人： Mirko Scholz , David Eric Tremouilles , Steven Thijs , Dimitri Linten
IPC分类号： G01R35/00
CPC分类号： G01R31/002 , G01R35/005
摘要： The present disclosure relates to a method for calibrating transient behaviour of an electrostatic discharge (ESD) test system. The system includes an ESD pulse generator and probe needles for applying a predetermined pulse on a device under test. The probe needles are connected to the ESD pulse generator via conductors. The test system includes measurement equipment for detecting transient behaviour of the device under test by simultaneously capturing voltage and current waveforms the device as a result of the pulse. The method comprises the steps of: (a) applying the ESD test system on a first known system with a first known impedance, (b) applying the ESD test system on a second known system with a known second impedance, and (c) determining calibration data for the transient behaviour the ESD test system on the basis of captured voltage and current waveforms, taking into account said known first and second impedances. In preferred embodiments the waveforms are transferred to the frequency domain for correlation.
摘要翻译：本公开涉及一种用于校准静电放电（ESD）测试系统的瞬态特性的方法。该系统包括用于在被测器件上施加预定脉冲的ESD脉冲发生器和探针。探针通过导体连接到ESD脉冲发生器。该测试系统包括用于通过同时捕获脉冲结果的电压和电流波形来检测被测器件的瞬态特性的测量设备。该方法包括以下步骤：（a）将ESD测试系统应用于具有第一已知阻抗的第一已知系统上，（b）将ESD测试系统应用于具有已知第二阻抗的第二已知系统上，以及（c）确定考虑到所述已知的第一和第二阻抗，基于捕获的电压和电流波形，ESD测试系统的瞬态特性的校准数据。在优选实施例中，波形被传送到频域以进行相关。

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