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11. 发明申请

US20090020887A1 SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090020887A1
公开(公告)日：2009-01-22
申请号：US12174192
申请日：2008-07-16
申请人： Shigeru MIZUNO , Takashi KURIHARA , Akinori SHIRAISHI , Kei MURAYAMA , Mitsutoshi HIGASHI
发明人： Shigeru MIZUNO , Takashi KURIHARA , Akinori SHIRAISHI , Kei MURAYAMA , Mitsutoshi HIGASHI
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L25/0657 , H01L21/6835 , H01L24/24 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/82 , H01L24/85 , H01L2224/24145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48465 , H01L2224/48471 , H01L2224/76152 , H01L2224/78 , H01L2224/85001 , H01L2225/06551 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/30105 , H01L2924/00 , H01L2224/4554
摘要： In a semiconductor apparatus in which plural semiconductor elements are stacked, metal wires whose one ends are connected to electrode terminals of the semiconductor elements are extended to the side surfaces of the semiconductor elements in an abutment state and the metal wires extended to the side surfaces of the semiconductor elements are bonded to a side surface wiring formed on side surfaces of the semiconductor elements by a conductive paste containing conductive particles.
摘要翻译：在层叠多个半导体元件的半导体装置中，一端与半导体元件的电极端子连接的金属线以邻接状态延伸到半导体元件的侧面，金属线延伸到半导体元件通过含有导电性粒子的导电性糊料与半导体元件的侧面形成的侧面配线接合。

12. 发明申请

US20090001571A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090001571A1
公开(公告)日：2009-01-01
申请号：US12146003
申请日：2008-06-25
申请人： Shigeru Mizuno , Takashi Kurihara
发明人： Shigeru Mizuno , Takashi Kurihara
IPC分类号： H01L23/488 , H01L21/60
CPC分类号： H01L24/81 , H01L2224/1134 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/73204 , H01L2224/81193 , H01L2224/81203 , H01L2224/81405 , H01L2224/81825 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/3511 , H01L2924/00 , H01L2924/00014
摘要： A method of manufacturing a semiconductor device in which a semiconductor element 10 is mounted on a substrate 20 through a flip-chip connection, includes the steps of cladding gallium as a bonding material 30 to a connecting pad 22 formed on a surface of the substrate 20, diffusing copper from the connecting pad 22 formed of the copper into the bonding material 30 through heating under vacuum, thereby bringing a state of a solid solution of the gallium and the copper, and aligning a connecting bump 12 formed on the semiconductor element 10 with the connecting pad 22 and bonding the connecting bump 12 to the connecting pad 22 through the bonding material 30 in a state of a solid solution under heating.
摘要翻译：通过倒装芯片连接将半导体元件10安装在基板20上的半导体器件的制造方法包括以下步骤：将形成在基板20的表面上的连接焊盘22作为接合材料30包覆镓通过在真空下加热将铜从铜连接焊盘22扩散到接合材料30中，从而使镓和铜的固溶状态，并使形成在半导体元件10上的连接凸块12与形成在半导体元件10上的连接凸块12与连接焊盘22，并且在加热下处于固溶状态下，通过接合材料30将连接凸块12接合到连接焊盘22。

13. 发明授权

US06872289B2 Thin film fabrication method and thin film fabrication apparatus 失效
标题翻译：薄膜制造方法和薄膜制造装置
公开(公告)号：US06872289B2
公开(公告)日：2005-03-29
申请号：US09799609
申请日：2001-03-07
申请人： Shigeru Mizuno , Makoto Satou , Manabu Tagami , Hideki Satou
发明人： Shigeru Mizuno , Makoto Satou , Manabu Tagami , Hideki Satou
IPC分类号： C23C14/34 , C23C14/35 , C23C16/52 , H01J37/34 , H01L21/285 , C23C16/00
CPC分类号： H01J37/32706 , C23C14/354 , H01J37/3405
摘要： A thin film is fabricated while causing ions in a plasma P to be incident by effecting biasing relative to the space potential of the plasma P by imparting a set potential to the surface of a substrate 9. A bias system 6 causes the substrate surface potential Vs to vary in pulse form by imposing an electrode imposed voltage Ve in pulse form on a bias electrode 23 which is in a dielectric block 22. The pulse frequency is lower than the oscillation frequency of ions in the plasma P, and the pulse period T, pulse width t and pulse height h are controlled by a control section 62 in a manner such that the incidence of ions is optimized. The imposed pulses are controlled in a manner such that the substrate surface potential Vs recovers to a floating potential Vf at the end of a pulse period T, and that the ion incidence energy temporarily crosses a thin film sputtering threshold value in a pulse period T.
摘要翻译：制造薄膜，同时使等离子体P中的离子通过相对于等离子体P的空间电位施加偏置而入射，通过赋予衬底9的表面设定电位。偏置系统6使衬底表面电位Vs 通过在介质块22中的偏置电极23上施加脉冲形式的电极施加的电压Ve来改变脉冲形式。脉冲频率低于等离子体P中的离子的振荡频率，脉冲周期T，脉冲宽度t和脉冲高度h由控制部分62以使得离子的入射被优化的方式控制。施加的脉冲以使得在脉冲周期T结束时基板表面电位Vs恢复到浮动电位Vf的方式被控制，并且离子入射能量在脉冲周期T中暂时跨越薄膜溅射阈值。

14. 发明授权

US06849945B2 Multi-layered semiconductor device and method for producing the same 失效
标题翻译：多层半导体器件及其制造方法
公开(公告)号：US06849945B2
公开(公告)日：2005-02-01
申请号：US09881005
申请日：2001-06-14
申请人： Michio Horiuchi , Takashi Kurihara , Shigeru Mizuno
发明人： Michio Horiuchi , Takashi Kurihara , Shigeru Mizuno
IPC分类号： H01L23/12 , H01L23/498 , H01L23/52 , H01L23/538 , H01L25/10 , H01L25/11 , H01L25/18 , H01L23/48
CPC分类号： H01L23/49816 , H01L23/5385 , H01L24/50 , H01L25/105 , H01L2225/1035 , H01L2225/1058 , H01L2924/07802 , H01L2924/00
摘要： To minimize a size of a semiconductor device and reduce a thickness thereof as well as improve the yield and lower the production cost in the production of a semiconductor package, a multi-layered semiconductor device is provided, wherein a film-like semiconductor package (10) incorporating therein a semiconductor chip (12) is disposed in a package accommodation opening (11a) of a circuit pattern layer to form a circuit board. A plurality of such circuit boards are layered together to electrically connect circuit patterns (13) of the circuit boards with each other via a low melting point metal (14) or lead beam bonding (13b).
摘要翻译：为了最小化半导体器件的尺寸并减小其厚度，并且提高了半导体封装的制造中的产量并降低了生产成本，提供了一种多层半导体器件，其中膜状半导体封装（10 ）设置在电路图案层的封装容纳开口（11a）中以形成电路板。多个这样的电路板层叠在一起，通过低熔点金属（14）或引线束接合（13b）将电路板的电路图案（13）彼此电连接。

15. 发明授权

US06518672B2 Multi-layer wiring board substrate and semiconductor device using the multi-layer wiring substrate 有权
标题翻译：多层布线基板和使用多层布线基板的半导体器件
公开(公告)号：US06518672B2
公开(公告)日：2003-02-11
申请号：US09880978
申请日：2001-06-14
申请人： Takashi Kurihara , Michio Horiuchi , Shigeru Mizuno , Yuka Tamadate
发明人： Takashi Kurihara , Michio Horiuchi , Shigeru Mizuno , Yuka Tamadate
IPC分类号： H01L2348
CPC分类号： H05K3/363 , H01L23/49805 , H01L23/4985 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06551 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H05K1/144 , H05K2201/0397 , H05K2201/10681
摘要： A multi-layer wiring substrate comprises: a plurality of wiring substrates, each of the substrates comprising a plate or sheet-like insulating layer and a wiring layer formed on only one of surfaces of the insulating layer; the plurality of wiring substrates being laminated in such a manner that the insulating layer and wiring layer are alternately arranged; at least a pair of said wiring layers arranged on respective surfaces of the insulating layer being electrically connected with each other by means of connecting portions formed so as to pass through the insulating layer; and the connecting portion comprises a part of the wiring layer which is extended into a region of an opening formed so as to pass through said insulating layer and a low-melting point metal disposed in the opening and electrically connecting the part of the wiring layer with a wiring substrate formed on an adjacent insulating layer of the laminated structure.
摘要翻译：多层布线基板包括：多个布线基板，每个基板包括板或片状绝缘层和仅形成在绝缘层的一个表面上的布线层; 所述多个布线基板以使得所述绝缘层和布线层交替布置的方式层叠; 布置在绝缘层的各个表面上的至少一对所述布线层通过形成为穿过绝缘层的连接部彼此电连接; 并且所述连接部分包括延伸到形成为穿过所述绝缘层的开口的区域中的所述布线层的一部分和布置在所述开口中的低熔点金属，并且将所述布线层的所述部分与形成在叠层结构的相邻绝缘层上的布线基板。

16. 发明授权

US06455786B1 Wiring board and manufacturing method thereof and semiconductor device 有权
标题翻译：接线板及其制造方法及半导体器件
公开(公告)号：US06455786B1
公开(公告)日：2002-09-24
申请号：US09539117
申请日：2000-03-30
申请人： Michio Horiuchi , Shigetsugu Muramatsu , Shigeru Mizuno , Takashi Kurihara
发明人： Michio Horiuchi , Shigetsugu Muramatsu , Shigeru Mizuno , Takashi Kurihara
IPC分类号： H05K116
CPC分类号： H01L23/3114 , H01L23/3107 , H01L23/49827 , H01L24/48 , H01L24/97 , H01L2224/05599 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01058 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/351 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A wiring board and electrode of a semiconductor element are connected with each other by the method of wire bonding, and problems arising from the thermal stress generated in the process of mounting are overcome. There is provided a wiring board comprising: a first face joined to an electrode forming face of a semiconductor element 10; and a second face on the opposite side of the first face, a wiring pattern 16 being formed on the second face, a land 24 joined to an external connecting terminal 22 being formed at one end of the wiring pattern, a wire bonding section 16a connected with a bonding wire 40 being formed at the other end of the wiring pattern, wherein the land 24 is supported by a buffer layer 34 for reducing the thermal stress generated when the semiconductor element, to which the wiring board is attached, is mounted via the external connecting terminals, and the wire bonding section 16a is supported by a bonding support layer 36 having an elastic modulus capable of allowing wire bonding.
摘要翻译：半导体元件的布线基板和电极通过引线接合的方式相互连接，克服了在安装过程中产生的热应力引起的问题。提供了一种布线板，包括：连接到半导体元件10的电极形成面的第一面; 和在第一面的相对侧的第二面，形成在第二面上的布线图案16，形成在布线图案的一端的与外部连接端子22接合的台面24，连接有引线接合部16a 其中接合线40形成在布线图案的另一端，其中，台肩24由缓冲层34支撑，用于减小当安装有布线板的半导体元件经由外部连接端子和引线接合部分16a由具有能够引线接合的弹性模量的接合支撑层36支撑。

17. 发明授权

US06407460B1 Multilayer circuit board 有权
标题翻译：多层电路板
公开(公告)号：US06407460B1
公开(公告)日：2002-06-18
申请号：US09616139
申请日：2000-07-13
申请人： Michio Horiuchi , Shigeru Mizuno
发明人： Michio Horiuchi , Shigeru Mizuno
IPC分类号： H01L2352
CPC分类号： H01L23/49838 , H01L2224/16 , H01L2224/16235 , H01L2924/15174 , H01L2924/15311 , H05K1/112 , H05K2201/09227 , H05K2201/10734
摘要： The present invention provides a multilayer circuit board for mounting thereon a semiconductor chip or other electronic elements having electrode terminals or other connection terminals which are arranged in a grid, staggered, or close-packed manner in an improved form to enable reduction in the number of the wiring layers for lead wiring lines, thereby facilitating the production of multilayer circuit boards and providing an improved product reliability. The multilayer circuit board comprises: a base board having a mounting surface for mounting thereon a semiconductor chip and/or other electronic elements having lattice-arranged connection terminals; connection terminal pads arranged on the mounting surface to form a plane lattice corresponding to the lattice arrangement of the connection terminals and having lattice sites each occupied by one of the connection terminal pads; lead wiring lines lying on the mounting surface and having one end connected to the connection terminal pads and the other end extending outwardly from the plane lattice; and the said plane lattice having a peripheral zone including periodic vacant lattice areas formed by vacant lattice sites occupied by no connection terminal pads.
摘要翻译：本发明提供了一种多层电路板，用于在其上安装半导体芯片或具有电极端子或其他连接端子的其他电子元件，电子端子或其他连接端子以改进的形式布置成格栅，交错或紧密堆叠的方式，以减少数量用于引线布线的布线层，从而便于生产多层电路板并提供改进的产品可靠性。多层电路板包括：基板，其具有用于安装其上的半导体芯片的安装表面和/或具有格子排列的连接端子的其它电子元件; 连接端子焊盘，其布置在所述安装表面上以形成与所述连接端子的格栅布置相对应的平面格子，并具有各自由所述连接端子焊盘之一占据的格子部位; 引线布线位于安装表面上，其一端连接到连接端子焊盘，另一端从平面格架向外延伸; 并且所述平面晶格具有包括由没有连接端子焊盘占据的空位网格形成的周期性空格格区域的周边区域。

18. 发明授权

US6129046A Substrate processing apparatus 失效
标题翻译：基板加工装置
公开(公告)号：US6129046A
公开(公告)日：2000-10-10
申请号：US795348
申请日：1997-02-04
申请人： Shigeru Mizuno , Masahito Ishihara , Kazuhito Watanabe , Nobuyuki Takahashi
发明人： Shigeru Mizuno , Masahito Ishihara , Kazuhito Watanabe , Nobuyuki Takahashi
IPC分类号： C23C14/50 , C23C16/44 , C23C16/455 , C23C16/458 , C23F4/00 , H01L21/203 , H01L21/205 , H01L21/285 , H01L21/302 , H01L21/3065 , H01L21/324 , C23C16/00
CPC分类号： C23C16/45521 , C23C16/4585 , C23C16/4586
摘要： The present invention provides a substrate processing apparatus having improved temperature distribution on a block heater and improved productivity. The substrate processing apparatus includes a reactor having an exhaust unit to form a vacuum environment therein for processing a surface of a substrate, a support member provided in the reactor, and gas introduction units for introducing reactive gases into the reactor, the substrate support member including a block heater. The block heater has upper, intermediate and lower members, which are placed one over another, the faying surfaces of the respective members being joined by diffusion bonding. A heating member is provided between the intermediate and lower members, and purge gas passages are formed between the intermediate and upper members.
摘要翻译：本发明提供一种具有改进的块加热器温度分布和提高生产率的基板处理装置。基板处理装置包括具有排气单元的反应器，用于在其中形成用于处理基板的表面的真空环境，设置在反应器中的支撑构件和用于将反应气体引入反应器的气体引入单元，所述基板支撑构件包括一个块加热器。块式加热器具有一个上下放置的上部，中间和下部构件，各个构件的接合表面通过扩散接合连接。加热构件设置在中间构件和下构件之间，并且在中间构件和上构件之间形成吹扫气体通道。

19. 发明授权

US5534072A Integrated module multi-chamber CVD processing system and its method for processing subtrates 失效
标题翻译：集成模块多室CVD处理系统及其处理方法
公开(公告)号：US5534072A
公开(公告)日：1996-07-09
申请号：US77687
申请日：1993-06-16
申请人： Shigeru Mizuno , Yoshihiro Katsumata , Nobuyuki Takahashi
发明人： Shigeru Mizuno , Yoshihiro Katsumata , Nobuyuki Takahashi
IPC分类号： C23C16/44 , C23C16/455 , C23C16/458 , C23C16/54 , C23C16/00
CPC分类号： C23C16/45519 , C23C16/4401 , C23C16/45521 , C23C16/4585 , C23C16/54 , Y10S414/135 , Y10S438/908
摘要： In a CVD processing system for depositing a blanket tungsten film, a distinct shadow is formed without causing any micro-peeling when the substrate fixture is separated from the substrate so as to prevent any blanket tungsten from being deposited on SiO.sub.2, thus reducing the occurrence of fine dust particles. A CVD processing system for depositing a blanket tungsten film, includes a susceptor (4); a ring chuck (9) for affixing the peripheral portion of a substrate (3) on the susceptor; reactive gas supply mechanisms (17, 18 and 19) for supplying reactive gas; and an exhaust mechanism (2) for exhausting unreacted gas and the like, wherein: the ring chuck has at least three point contact members (10) in contact with the peripheral portion of the substrate; the point contact members are provided at positions outside the inner periphery of the ring chuck; a gap (11) is formed at the point contact members between the ring chuck and the substrate; and purge gas supply mechanisms (20 and 21) are provided to blow off purge gas through the gap in order to prevent reactive gas from entering the gap (11). A ratio of the size of the gap to the flow rate of purge gas is set to such an optimum value as to satisfy a condition in which the position of the peripheral portion of the thin film coincides with the position of the inner periphery of the ring chuck.
摘要翻译：在用于沉积覆盖钨膜的CVD处理系统中，当衬底夹具与衬底分离时，形成不同的阴影，而不会发生任何微剥离，以防止任何覆盖的钨沉积在SiO 2上，从而减少细尘粒子。一种用于沉积覆盖钨膜的CVD处理系统，包括基座（4）; 环形卡盘（9），用于将基板（3）的周边部分固定在基座上; 用于供应反应性气体的反应气体供应机构（17,18和19）以及用于排出未反应气体等的排气机构（2），其中：所述环卡盘具有与所述基板的周边部分接触的至少三点接触构件（10）点接触构件设置在环卡盘的内周的外侧的位置; 在环卡盘和基板之间的点接触构件处形成间隙（11）; 并且提供吹扫气体供给机构（20和21）以吹扫通过间隙的吹扫气体，以防止反应性气体进入间隙（11）。将间隙尺寸与吹扫气体的流量的比率设定为最佳值，以满足薄膜的周边部分的位置与环的内周的位置一致的条件卡盘

20. 发明授权

US10519000B2 Sheet processing apparatus and image forming system including multiple folding members 有权
公开(公告)号：US10519000B2
公开(公告)日：2019-12-31
申请号：US16116161
申请日：2018-08-29
申请人： Ken Sawada , Shigeru Mizuno , Hiroyuki Kuno , Takuya Fukuhara
发明人： Ken Sawada , Shigeru Mizuno , Hiroyuki Kuno , Takuya Fukuhara
IPC分类号： B65H45/14
摘要： A sheet processing apparatus that forms a folding line on a sheet includes first and second folding rollers that form a folding line on the sheet by rotating a bent sheet while pinching from sheet surfaces and a first pressing unit that presses the second folding roller against the first folding roller in an arbitrary portion in a rotating shaft direction of the second folding roller.

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