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11. 发明授权

US5506182A Modified zeolite Y catalyst composition 失效
标题翻译：改性沸石Y催化剂组合物
公开(公告)号：US5506182A
公开(公告)日：1996-04-09
申请号：US217985
申请日：1994-03-25
申请人： Koji Yamagishi , Satoshi Nakai , Akira Iino
发明人： Koji Yamagishi , Satoshi Nakai , Akira Iino
IPC分类号： B01J29/06 , B01J29/08 , B01J29/14 , B01J29/16 , B01J29/78 , C01B39/06 , C01B39/24
CPC分类号： B01J29/061 , B01J29/084 , B01J29/146 , B01J29/7807 , B01J2229/42
摘要： A catalyst composition comprising a modified zeolite and a binder mixed with a high degree of mixing has high hydrothermal resistance and exhibits high activities in various catalytic reactions, including various hydrocarbon-conversion reactions, and the catalyst composition is prepared by mixing a slurry of a modified zeolite and a slurry of a binder material.
摘要翻译：包含改性沸石和混合高混合物的粘合剂的催化剂组合物具有高耐水热性，并且在各种催化反应中显示出高活性，包括各种烃转化反应，并且催化剂组合物通过将经修饰的沸石和粘合剂材料的浆料。

12. 发明授权

US08884375B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08884375B2
公开(公告)日：2014-11-11
申请号：US12561719
申请日：2009-09-17
申请人： Satoshi Nakai , Masato Suga , Jusuke Ogura
发明人： Satoshi Nakai , Masato Suga , Jusuke Ogura
IPC分类号： H01L29/76 , H01L21/336 , H01L21/8238 , H01L21/02 , H01L29/78 , H01L29/66
CPC分类号： H01L21/02225 , H01L21/8238 , H01L21/823807 , H01L29/665 , H01L29/7843
摘要： A disclosed semiconductor integrated circuit device includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.
摘要翻译：所公开的半导体集成电路器件包括半导体衬底; 以及设置在半导体衬底上的多个半导体元件。半导体元件包括n沟道MOS晶体管和p沟道MOS晶体管。 n沟道MOS晶体管由拉伸应力膜覆盖，并且p沟道MOS晶体管被压缩应力膜覆盖。在半导体衬底的表面上设置整个表面被拉伸应力膜和压缩应力膜的组合覆盖的虚拟区域。

13. 发明申请

US20100001350A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20100001350A1
公开(公告)日：2010-01-07
申请号：US12561719
申请日：2009-09-17
申请人： Satoshi Nakai , Masato Suga , Jusuke Ogura
发明人： Satoshi Nakai , Masato Suga , Jusuke Ogura
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/302
CPC分类号： H01L21/02225 , H01L21/8238 , H01L21/823807 , H01L29/665 , H01L29/7843
摘要： A disclosed semiconductor integrated circuit device includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.
摘要翻译：所公开的半导体集成电路器件包括半导体衬底; 以及设置在半导体衬底上的多个半导体元件。半导体元件包括n沟道MOS晶体管和p沟道MOS晶体管。 n沟道MOS晶体管由拉伸应力膜覆盖，并且p沟道MOS晶体管被压缩应力膜覆盖。在半导体衬底的表面上设置整个表面被拉伸应力膜和压缩应力膜的组合覆盖的虚拟区域。

14. 发明申请

US20090166746A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090166746A1
公开(公告)日：2009-07-02
申请号：US12342453
申请日：2008-12-23
申请人： Junichi Mitani , Satoshi Nakai , Kazushi Fujita
发明人： Junichi Mitani , Satoshi Nakai , Kazushi Fujita
IPC分类号： H01L21/762 , H01L27/088 , G06F17/50
CPC分类号： H01L21/823456 , H01L21/823412 , H01L27/0207 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a first and a second active regions of a first conductivity type disposed on a semiconductor substrate, a third and a fourth active regions of a second conductivity type disposed on the semiconductor substrate, the second and the fourth active regions having sizes larger than those of the first and the third active regions respectively, a first electroconductive pattern disposed adjacent to the first active region and having a first width, a second electroconductive pattern disposed adjacent to the second active region and having a second width larger than the first width, a third electroconductive pattern disposed adjacent to the third active region and having a third width; and a fourth electroconductive pattern disposed adjacent to the fourth active region and having a fourth width smaller than the third width.
摘要翻译：半导体器件具有设置在半导体衬底上的第一导电类型的第一和第二有源区，设置在半导体衬底上的第二导电类型的第三和第四有源区，第二和第四有源区的尺寸较大分别设置为与第一有源区域相邻并且具有第一宽度的第一导电图案，与第二有源区域相邻设置并且具有大于第一宽度的第二宽度的第二导电图案第三导电图案，其布置成与所述第三有源区相邻并且具有第三宽度; 以及第四导电图案，其布置成与所述第四有源区相邻并且具有小于所述第三宽度的第四宽度。

15. 发明申请

US20050106837A1 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20050106837A1
公开(公告)日：2005-05-19
申请号：US10844497
申请日：2004-05-13
申请人： Satoshi Nakai , Jun Sakuma , Mitsugu Tajima
发明人： Satoshi Nakai , Jun Sakuma , Mitsugu Tajima
IPC分类号： H01L21/76 , H01L21/336 , H01L21/762 , H01L21/84 , H01L27/08 , H01L27/12 , H01L29/786 , H01L21/00 , H01L21/8234
CPC分类号： H01L29/66772 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78609 , H01L29/78654
摘要： A method for manufacturing a semiconductor device includes: forming a first photoresist pattern on a second hard mask by use of ArF; forming first and second openings in the second hard mask by use of the first photoresist pattern as an etching mask; forming third and fourth openings in a first hard mask under the first and second openings; forming a partial trench (first trench) and a trench for a full trench (second trench) in an SOI substrate (semiconductor substrate) under the first and second openings; and forming the trench for a full trench into a full trench by etching the trench for a full trench through the fourth opening exposed through a third window of a second photoresist pattern.
摘要翻译：一种制造半导体器件的方法包括：通过使用ArF在第二硬掩模上形成第一光致抗蚀剂图案; 通过使用第一光致抗蚀剂图案作为蚀刻掩模在第二硬掩模中形成第一和第二开口; 在第一和第二开口下方的第一硬掩模中形成第三和第四开口; 在第一和第二开口下方的SOI衬底（半导体衬底）中形成用于全沟槽（第二沟槽）的部分沟槽（第一沟槽）和沟槽; 以及通过蚀刻通过穿过第二光致抗蚀剂图案的第三窗口暴露的第四开口的全沟槽的沟槽，将全沟槽的沟槽形成全沟槽。

16. 发明授权

US06729926B2 Method for making magnetrons 失效
标题翻译：制造磁控管的方法
公开(公告)号：US06729926B2
公开(公告)日：2004-05-04
申请号：US10020766
申请日：2001-12-12
申请人： Noriyuki Murao , Kazuki Miki , Satoshi Nakai , Setsuo Hasegawa , Noriyuki Okada
发明人： Noriyuki Murao , Kazuki Miki , Satoshi Nakai , Setsuo Hasegawa , Noriyuki Okada
IPC分类号： H01J914
CPC分类号： H01J23/165 , H01J2223/16 , H01J2225/50 , H01J2225/587
摘要： A magnetron has an anode cylinder, a plurality of vanes arranged radially within the anode cylinder, a magnetic piece disposed at an open end section of the anode cylinder, an anode vacuum container including a metal container disposed to cover an upper surface of the magnetic piece, a cathode disposed along a central axis of the vacuum container, and an antenna externally discharging microwaves. The magnetic piece and the metal container are placed, in that order, on a shelf formed inwardly on a thin end section projecting from the open end section of the anode cylinder. When tightly welding the thin end section, a predetermined number of projections, projecting inwardly from the thin end section of the anode cylinder, loosely secure an outer perimeter bend of the metal container. The metal container is then accurately tightly welded to the anode cylinder without the metal container shifting off-center.
摘要翻译：磁控管具有阳极筒，在阳极筒内径向设置的多个叶片，设置在阳极筒的开口端部的磁性片，阳极真空容器，其包括设置成覆盖磁性片的上表面的金属容器，沿着真空容器的中心轴设置的阴极和从外部排出微波的天线。磁片和金属容器依次放置在从阳极圆筒的开口端突出的薄端部分上向内形成的搁板上。当紧密焊接薄端部时，从阳极筒的薄端部向内突出的预定数量的突起松动地固定金属容器的外周弯曲部。然后将金属容器准确地紧密地焊接到阳极筒，而不会使金属容器偏离中心。

17. 发明授权

US06633131B2 Magnetron 失效
标题翻译：磁控管
公开(公告)号：US06633131B2
公开(公告)日：2003-10-14
申请号：US09924386
申请日：2001-08-08
申请人： Noriyuki Murao , Kazuki Miki , Setsuo Hasegawa , Noriyuki Okada , Satoshi Nakai
发明人： Noriyuki Murao , Kazuki Miki , Setsuo Hasegawa , Noriyuki Okada , Satoshi Nakai
IPC分类号： H01J2550
CPC分类号： H01J23/14 , H01J25/587
摘要： A ring-shaped depressed groove 11 is formed between a joining surface 10 of a stem insulating material 6 with a tubular metal container 16 and a joining surface 9 with cathode leads 2a and 2b. A metallized layer 8, formed at joining surface 9 and joining surface 10, is separated from edges 12 and 13 of ring-shaped depressed groove 11. The resulting magnetron reliably prevents discharges generated between the joining surface of the stem insulating material, with the tubular metal container, and the joining surface, with the cathode leads.
摘要翻译：在茎绝缘材料 10 之间形成环形凹槽 11 > 6 与管状金属容器 16 和接合表面 9 hIL> 2 a 和 2 在接合表面 9 上形成的金属层 8，，并连接表面 PDAT> 10，与环形凹槽的边缘 12 和 13 11。所得的磁控管可靠地防止在杆状绝缘材料的接合表面与管状金属容器之间产生的放电和接合表面与阴极引线之间产生的放电。

18. 发明授权

US5207893A Hydrocracking process employing a novel iron-containing aluminosilicate 失效
标题翻译：加氢裂化工艺采用新型含铁铝硅酸盐
公开(公告)号：US5207893A
公开(公告)日：1993-05-04
申请号：US833709
申请日：1992-02-11
申请人： Ryuichiro Iwamoto , Satoshi Nakai
发明人： Ryuichiro Iwamoto , Satoshi Nakai
IPC分类号： B01J29/072 , B01J29/14 , C10G47/20
CPC分类号： B01J29/146 , B01J29/072 , C10G47/20 , B01J2229/18 , B01J2229/24 , B01J2229/36 , B01J2229/37
摘要： A process for hydrocracking heavy oil which comprises hydrocracking the heavy oil in the presence of a catalyst comprising a support of 10 to 90% by weight of an iron-containing aluminosilicate and 90 to 10% by weight of an inorganic oxide, and at least one metal belonging to Group VIB of the Periodic Table and at least one metal belonging to Group VIII deposited on the support. The iron-containing aluminosilicate has a composition of the formula expressed as oxides: aFe.sub.2 O.sub.3 .multidot.Al.sub.2 O.sub.3 .multidot.bSiO.sub.2 .multidot.nH.sub.2 O wherein n is a real number of 0 to 30, and a and b are real numbers satisfying the following relationships: 15
摘要翻译：一种加氢裂化重油的方法，其中包括在催化剂存在下加氢裂解重质油，该催化剂包含10至90重量％的含铁硅铝酸盐和90至10重量％的无机氧化物的载体和至少一种属于元素周期表第VIB族的金属和至少一种属于第VIII族的金属沉积在载体上。含铁铝硅酸盐具有以氧化物表示的分子式：aFe 2 O 3 x Al 2 O 3 xbSiO 2·xH 2 O，其中n为0〜30的实数，a和b为满足以下关系的实数：15

19. 发明授权

US5188058A Uniform gas flow CVD apparatus 失效
标题翻译：均匀气流CVD装置
公开(公告)号：US5188058A
公开(公告)日：1993-02-23
申请号：US902661
申请日：1992-06-22
申请人： Satoshi Nakai
发明人： Satoshi Nakai
IPC分类号： C30B25/14 , C23C16/44 , C23C16/455 , C23C16/48 , H01L21/205 , H01L21/31
CPC分类号： C23C16/45565 , C23C16/455 , C23C16/45508 , C23C16/45519 , C23C16/481
摘要： A CVD apparatus comprising a reaction chamber in which reaction gas is supplied from above the substrate supported on the susceptor plate and exhausted uniformly from a plurality of circumferentially spaced gas exits, and infrared light heats the substrate from below the substrate via an infrared light transparent window arranged between the source of infrared light and the susceptor plate. A second infrared light transparent window with a central opening is arranged between the first infrared light transparent window and the susceptor plate. Nitrogen gas or an inert gas is supplied from a portion between the first and second infrared light transparent windows and flows through a plurality of circumferentially spaced gas passages arranged at the juncture of the susceptor plate and the peripheral wall of the reaction chamber to the gas exits. The gas passages are coordinated with the gas exits so that the flow of the reaction gas is less disturbed by the flow of the second gas.
摘要翻译：一种CVD装置，包括反应室，其中反应气体从支撑在基座板上的基板的上方供应并从多个周向间隔开的气体出口均匀排出，并且红外光通过红外光透明窗从基板下方加热基板布置在红外光源和基座板之间。具有中央开口的第二红外透光窗设置在第一红外光透明窗和基座板之间。氮气或惰性气体从第一和第二红外光透明窗口之间的部分供应，并且流过布置在基座板和反应室的周壁的接合处的多个周向隔开的气体通道到气体出口。气体通道与气体出口协调，使得反应气体的流动受到第二气体的流动的干扰较小。

20. 发明授权

US07910957B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07910957B2
公开(公告)日：2011-03-22
申请号：US12342453
申请日：2008-12-23
申请人： Junichi Mitani , Satoshi Nakai , Kazushi Fujita
发明人： Junichi Mitani , Satoshi Nakai , Kazushi Fujita
IPC分类号： H01L23/52
CPC分类号： H01L21/823456 , H01L21/823412 , H01L27/0207 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a first and a second active regions of a first conductivity type disposed on a semiconductor substrate, a third and a fourth active regions of a second conductivity type disposed on the semiconductor substrate, the second and the fourth active regions having sizes larger than those of the first and the third active regions respectively, a first electroconductive pattern disposed adjacent to the first active region and having a first width, a second electroconductive pattern disposed adjacent to the second active region and having a second width larger than the first width, a third electroconductive pattern disposed adjacent to the third active region and having a third width; and a fourth electroconductive pattern disposed adjacent to the fourth active region and having a fourth width smaller than the third width.
摘要翻译：半导体器件具有设置在半导体衬底上的第一导电类型的第一和第二有源区，设置在半导体衬底上的第二导电类型的第三和第四有源区，第二和第四有源区的尺寸较大分别设置为与第一有源区域相邻并且具有第一宽度的第一导电图案，与第二有源区域相邻设置并且具有大于第一宽度的第二宽度的第二导电图案第三导电图案，其布置成与所述第三有源区相邻并且具有第三宽度; 以及第四导电图案，其布置成与所述第四有源区相邻并且具有小于所述第三宽度的第四宽度。

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