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11. 发明授权

US08000139B2 Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general purpose CMOS technology with thick gate oxide 有权
标题翻译：多时间可编程（MTP）PMOS浮动栅极非易失性存储器件，用于具有厚栅极氧化物的通用CMOS技术
公开(公告)号：US08000139B2
公开(公告)日：2011-08-16
申请号：US12430007
申请日：2009-04-24
申请人： Alexander Kalnitsky , Michael D. Church
发明人： Alexander Kalnitsky , Michael D. Church
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.
摘要翻译：根据实施例的多时间可编程（MTP）存储单元包括浮置栅极PMOS晶体管，高电压NMOS晶体管和n阱电容器。浮置栅极PMOS晶体管包括形成存储单元的第一端子，漏极和栅极的源极。高电压NMOS晶体管包括连接到地的源极，连接到PMOS晶体管的漏极的延伸漏极和形成存储器单元的第二端子的栅极。 n阱电容器包括连接到PMOS晶体管的栅极的第一端子和形成存储器单元的第三端子的第二端子。浮置栅极PMOS晶体管可以存储逻辑状态。可以将组合的电压施加到存储单元的第一，第二和第三端子，以编程，禁止程序，读取和擦除逻辑状态。

12. 发明申请

US20110182126A1 FLASH MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
标题翻译：基于盖板的非易失性记忆体的闪存存储阵列
公开(公告)号：US20110182126A1
公开(公告)日：2011-07-28
申请号：US13080814
申请日：2011-04-06
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
IPC分类号： G11C16/16
CPC分类号： G11C16/0416
摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：闪存阵列包括以行和列的矩阵组织的多个存储单元。每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。多个字线各自电连接到相应行中的每个存储器单元中的电容器。第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。多个高压存取晶体管分别电连接到第一组位线中的位线。第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

13. 发明申请

US20110116318A1 MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
公开(公告)号：US20110116318A1
公开(公告)日：2011-05-19
申请号：US13012361
申请日：2011-01-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/04
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

14. 发明授权

US07944745B2 Flash memory array of floating gate-based non-volatile memory cells 有权
标题翻译：基于浮动栅极的非易失性存储单元的闪存阵列
公开(公告)号：US07944745B2
公开(公告)日：2011-05-17
申请号：US12711520
申请日：2010-02-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0416
摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：闪存阵列包括以行和列的矩阵组织的多个存储单元。每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。多个字线各自电连接到相应行中的每个存储器单元中的电容器。第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。多个高压存取晶体管分别电连接到第一组位线中的位线。第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

15. 发明申请

US20100038726A1 RADIATION HARDENED DEVICE 失效
公开(公告)号：US20100038726A1
公开(公告)日：2010-02-18
申请号：US12372893
申请日：2009-02-18
申请人： Stephen J. GAUL , Michael D. Church , Brent R. Doyle
发明人： Stephen J. GAUL , Michael D. Church , Brent R. Doyle
IPC分类号： H01L29/772 , H01L21/30
CPC分类号： H01L27/088 , H01L21/761 , H01L21/823481 , H01L29/1083
摘要： A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.

16. 发明授权

US07224074B2 Active area bonding compatible high current structures 有权
标题翻译：有源区粘合兼容高电流结构
公开(公告)号：US07224074B2
公开(公告)日：2007-05-29
申请号：US11305987
申请日：2005-12-19
申请人： John T Gasner , Michael D Church , Sameer D Parab , Paul E Bakeman, Jr. , David A Decrosta , Robert Lomenic , Chris A McCarty
发明人： John T Gasner , Michael D Church , Sameer D Parab , Paul E Bakeman, Jr. , David A Decrosta , Robert Lomenic , Chris A McCarty
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L24/05 , H01L23/528 , H01L23/53295 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05082 , H01L2224/05166 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/01007 , H01L2224/45099
摘要： An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.
摘要翻译：一个集成电路，具有一个接合焊盘下的电路。在一个实施例中，集成电路包括衬底，顶部导电层，一个或多个中间导电层，绝缘材料和器件层。顶部导电层具有至少一个焊盘和相对刚性材料的子层。一个或多个中间导电层形成在顶部导电层和基底之间。绝缘材料层分离导电层。此外，绝缘材料层的一层相对较硬，并且位于顶部导电层和最靠近顶部导电层的中间导电层之间。器件形成在集成电路中。此外，至少最靠近顶部导电层的中间导电层适用于接合焊盘下的选择器件的功能互连。

17. 发明授权

US5994755A Analog-to-digital converter and method of fabrication 失效
标题翻译：模数转换器和制造方法
公开(公告)号：US5994755A
公开(公告)日：1999-11-30
申请号：US739898
申请日：1996-10-30
申请人： Glenn Alan DeJong , Akira Ito , Choong-Sun Rhee , Jeffrey Johnston , Michael D. Church , Kantilal Bacrania
发明人： Glenn Alan DeJong , Akira Ito , Choong-Sun Rhee , Jeffrey Johnston , Michael D. Church , Kantilal Bacrania
IPC分类号： G05F3/26 , G05F3/30 , G11C5/14 , G11C27/02 , H01L27/02 , H01L27/06 , H03F1/52 , H03F3/50 , H03G1/00 , H03K5/15 , H03K17/22 , H03M1/16 , H03M1/36
CPC分类号： G05F3/30 , G05F3/262 , G11C27/026 , G11C5/143 , H01L27/0214 , H01L27/0623 , H01L27/0688 , H03F1/523 , H03F3/505 , H03G1/0082 , H03K17/223 , H03K5/15 , H03M1/162 , H03F2200/294 , H03K2217/0018 , H03M1/365
摘要： An integrated circuit has a pseudosubstrate 6060 with an isolation moat 9505. Substrate 6001 has one conductivity and a subcircuit region 6060 has an opposite conductivity. Digital CMOS devices are formed in the subcircuit over region 6060 and operate between zero to +5 volts. Analog devices are formed over the rest of the substrate and operate between plus and minus 5 volts. The moat 9505 isolates the digital CMOS devices from the analog devices.
摘要翻译：集成电路具有带有隔离沟槽9505的伪衬底6060.衬底6001具有一个导电性，并且子电路区域6060具有相反的导电性。数字CMOS器件形成在子电路区域6060上，并在零到+5伏特之间工作。模拟器件形成在衬底的其余部分上，并在正负5伏之间工作。护城河9505将数字CMOS设备与模拟设备隔离开来。

18. 发明授权

US09147613B2 Method of forming an insulator layer in a semiconductor structure and structures resulting therefrom 有权
标题翻译：在半导体结构中形成绝缘体层的方法及由此产生的结构
公开(公告)号：US09147613B2
公开(公告)日：2015-09-29
申请号：US12942516
申请日：2010-11-09
申请人： Michael D. Church
发明人： Michael D. Church
IPC分类号： H01L21/8232 , H01L21/8234 , H01L27/06 , H01L27/08 , H01L27/088
CPC分类号： H01L21/823462 , H01L21/823468 , H01L27/0629 , H01L27/0805 , H01L27/088
摘要： An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a first semiconductor substructure over a semiconductor substrate, forming a first spacer layer over the first semiconductor substructure and the semiconductor substrate, and forming a second semiconductor substructure over at least a portion of the first spacer layer.
摘要翻译：公开了电子系统，半导体结构的制造方法和一个或多个半导体结构。例如，公开了一种制造半导体结构的方法，其包括在半导体衬底上形成第一半导体子结构，在第一半导体子结构和半导体衬底之上形成第一间隔层，并至少形成第二半导体子结构第一间隔层的一部分。

19. 发明申请

US20110140232A1 METHODS OF FORMING A THERMAL CONDUCTION REGION IN A SEMICONDUCTOR STRUCTURE AND STRUCTURES RESULTING THEREFROM 审中-公开
标题翻译：在半导体结构中形成导热区域的方法和结果对其结构的影响
公开(公告)号：US20110140232A1
公开(公告)日：2011-06-16
申请号：US12967246
申请日：2010-12-14
申请人： Stephen J. Gaul , Michael D. Church , Rick Carlton Jerome
发明人： Stephen J. Gaul , Michael D. Church , Rick Carlton Jerome
IPC分类号： H01L23/58 , H01L21/76
CPC分类号： H01L21/76283 , H01L23/3677 , H01L23/3732 , H01L23/3735 , H01L25/065 , H01L2225/06589 , H01L2924/0002 , H01L2924/00
摘要： An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a semiconductor layer over a thermal conduction layer, forming an isolation region over the thermal conduction layer, and forming a thermal conduction region in the isolation region.
摘要翻译：公开了电子系统，半导体结构的制造方法和一个或多个半导体结构。例如，公开了半导体结构的制造方法，其包括在导热层上形成半导体层，在导热层上形成隔离区域，并在隔离区域形成导热区域。

20. 发明申请

US20110116319A1 MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
公开(公告)号：US20110116319A1
公开(公告)日：2011-05-19
申请号：US13012381
申请日：2011-01-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/26
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

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