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11. 发明授权

US08889501B2 Methods for forming MOS devices with raised source/drain regions 有权
标题翻译：用于形成具有升高的源极/漏极区域的MOS器件的方法
公开(公告)号：US08889501B2
公开(公告)日：2014-11-18
申请号：US13486240
申请日：2012-06-01
申请人： Harry-Hak-Lay Chuang , Sin-Hua Wu , Chung-Hau Fei , Ming Zhu , Bao-Ru Young , Yen-Ru Lee , Chii-Horng Li , Tze-Liang Lee
发明人： Harry-Hak-Lay Chuang , Sin-Hua Wu , Chung-Hau Fei , Ming Zhu , Bao-Ru Young , Yen-Ru Lee , Chii-Horng Li , Tze-Liang Lee
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/11
CPC分类号： H01L27/1116 , H01L21/823807 , H01L21/823814
摘要： A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor.
摘要翻译：一种方法包括在半导体衬底上形成第一器件的第一栅极堆叠，以及在半导体衬底上形成第二MOS器件的第二栅极堆叠。执行第一外延以形成用于第二MOS器件的源/漏应力源，其中源极/漏极应力器与第二栅极堆叠相邻。执行第二外延以同时形成第一硅层和第二硅层，其中第一硅层位于半导体衬底的第一部分之上并且与第一栅极堆叠相邻。第二硅层与源极/漏极应力源重叠。

12. 发明授权

US08801471B2 USB connector assembly 有权
标题翻译： USB连接器总成
公开(公告)号：US08801471B2
公开(公告)日：2014-08-12
申请号：US13664609
申请日：2012-10-31
申请人： Zhi-Ming Zhu , Ting Wang , Dan Yu
发明人： Zhi-Ming Zhu , Ting Wang , Dan Yu
IPC分类号： H01R24/00
CPC分类号： H01R13/6271 , H01R12/79
摘要： A connector assembly includes a USB socket and a USB connector. The USB socket includes a housing and at least one engaging protrusion protruding from an inner surface of the housing. The USB connector includes a holding portion; a header adapted to be plugged into the USB socket which extends from a first end of the holding portion along a first direction; and a plurality of cables, extending from a second end of the holding portion along a second direction substantially perpendicular to the first direction. At least one groove is defined in the header for receiving the at least one engaging protrusion and preventing the header from accidentally disengaging from the USB socket.
摘要翻译：连接器组件包括USB插座和USB连接器。 USB插座包括壳体和从壳体的内表面突出的至少一个接合突起。 USB连接器包括保持部分; 适于插入从所述保持部分的第一端沿着第一方向延伸的所述USB插座的插头; 以及从所述保持部分的第二端沿着基本上垂直于所述第一方向的第二方向延伸的多根电缆。在集管中限定有至少一个槽，用于容纳至少一个接合突起并防止集管偶然脱离USB插座。

13. 发明授权

US08772114B2 Metal gate semiconductor device and method of fabricating thereof 有权
标题翻译：金属栅极半导体器件及其制造方法
公开(公告)号：US08772114B2
公开(公告)日：2014-07-08
申请号：US13434969
申请日：2012-03-30
申请人： Hak-Lay Chuang , Ming Zhu , Hui-Wen Lin , Bao-Ru Young
发明人： Hak-Lay Chuang , Ming Zhu , Hui-Wen Lin , Bao-Ru Young
IPC分类号： H01L21/8234
CPC分类号： H01L29/4966 , H01L21/823842 , H01L27/092 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： A method of semiconductor fabrication including forming a first work function metal layer on a first region of the substrate and forming a metal layer on the first work function metal layer and on a second region of the substrate. A dummy layer is formed on the metal layer. The layers are then patterned to form a first gate structure in the first region and a second gate structure in the second region of the substrate. The dummy layer is then removed to expose the metal layer, which is treated. The treatment may be an oxygen treatment that allows the metal layer to function as a second work function layer.
摘要翻译：一种半导体制造方法，包括在所述基板的第一区域上形成第一功函数金属层，并在所述第一功函数金属层上和所述基板的第二区域上形成金属层。在金属层上形成虚设层。然后将这些层图案化以在第一区域中形成第一栅极结构，在衬底的第二区域中形成第二栅极结构。然后去除虚拟层以暴露被处理的金属层。处理可以是允许金属层用作第二功函数层的氧处理。

14. 发明授权

US08753931B2 Cost-effective gate replacement process 有权
标题翻译：具有成本效益的门更换过程
公开(公告)号：US08753931B2
公开(公告)日：2014-06-17
申请号：US13440848
申请日：2012-04-05
申请人： Ming Zhu , Jyun-Ming Lin , Wei Cheng Wu , Bao-Ru Young , Hak-Lay Chuang
发明人： Ming Zhu , Jyun-Ming Lin , Wei Cheng Wu , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/092
CPC分类号： H01L29/4941 , H01L21/28088 , H01L21/283 , H01L21/28518 , H01L21/76814 , H01L21/76843 , H01L21/76855 , H01L21/823443 , H01L21/82345 , H01L21/823842 , H01L21/82385 , H01L27/092 , H01L27/0922 , H01L29/401 , H01L29/4236 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成第一栅极结构和第二栅极结构。第一和第二栅极结构各自包括位于衬底上方的高k电介质层，位于高k电介质层上方的覆盖层，位于覆盖层上方的N型功函数金属层和位于超过N型功函金属层。该方法包括在衬底，第一栅极结构和第二栅极结构之上形成层间电介质（ILD）层。该方法包括抛光ILD层，直到ILD层的表面与第一栅极结构和第二栅极结构的表面基本上共面。该方法包括用金属栅极替换第二栅极结构的部分。然后对半导体器件执行硅化处理。

15. 发明授权

US08749579B2 Pixel-feature hybrid fusion for PET/CT images 有权
标题翻译：用于PET / CT图像的像素特征混合融合
公开(公告)号：US08749579B2
公开(公告)日：2014-06-10
申请号：US13145135
申请日：2009-12-23
申请人： Yang-Ming Zhu , Charles A. Nortmann
发明人： Yang-Ming Zhu , Charles A. Nortmann
IPC分类号： G09G5/00
CPC分类号： G06T11/001 , A61B6/037 , G06T15/503
摘要： An image display method comprises: color coding a second image respective to an intensity spectrum with a portion or portions of the intensity spectrum set to be transparent to generate a color coded second image; combining a first image and the color coded second image to generate a fused image; and displaying the fused image. An image display system comprises: an image generating module configured to generate an image by color coding an input image in accordance with a colormap assigning colors to intensities of an intensity spectrum; a colormap modifying module configured to select a portion of the intensity spectrum to be transparent; and a display configured to display the generated image.
摘要翻译：一种图像显示方法包括：对强度谱进行颜色编码，其中所述强度谱的部分或部分设置为透明的，以产生颜色编码的第二图像; 组合第一图像和所述颜色编码的第二图像以生成融合图像; 并显示融合图像。一种图像显示系统，包括：图像生成模块，被配置为根据将颜色分配给强度谱强度的色彩图像，对输入图像进行彩色编码来生成图像; 配置为选择所述强度谱的一部分是透明的色彩变换模块; 以及被配置为显示所生成的图像的显示器。

16. 发明授权

US08703595B2 N/P boundary effect reduction for metal gate transistors 有权
标题翻译：金属栅极晶体管的N / P边界效应降低
公开(公告)号：US08703595B2
公开(公告)日：2014-04-22
申请号：US13299152
申请日：2011-11-17
申请人： Hak-Lay Chuang , Cheng-Cheng Kuo , Ching-Che Tsai , Ming Zhu , Bao-Ru Young
发明人： Hak-Lay Chuang , Cheng-Cheng Kuo , Ching-Che Tsai , Ming Zhu , Bao-Ru Young
IPC分类号： H01L21/336
CPC分类号： H01L27/0207 , H01L21/0274 , H01L21/28123 , H01L21/32139 , H01L21/823456 , H01L27/092 , H01L29/41775 , H01L29/42356 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate. The dummy gates extend along a first axis. The method includes forming a masking layer over the dummy gates. The masking layer defines an elongate opening extending along a second axis different from the first axis. The opening exposes first portions of the dummy gates and protects second portions of the dummy gates. A tip portion of the opening has a width greater than a width of a non-tip portion of the opening. The masking layer is formed using an optical proximity correction (OPC) process. The method includes replacing the first portions of the dummy gates with a plurality of first metal gates. The method includes replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成多个虚拟栅极。虚拟门沿着第一轴延伸。该方法包括在伪栅极上形成掩模层。掩蔽层限定沿着不同于第一轴线的第二轴线延伸的细长开口。开口暴露虚拟门的第一部分并保护虚拟门的第二部分。开口的尖端部分的宽度大于开口的非尖端部分的宽度。使用光学邻近校正（OPC）工艺形成掩模层。该方法包括用多个第一金属栅极替换伪栅极的第一部分。该方法包括用与第一金属栅极不同的多个第二金属栅极替换伪栅极的第二部分。

17. 发明授权

US08698252B2 Device for high-K and metal gate stacks 有权
标题翻译：高K和金属栅极堆叠的器件
公开(公告)号：US08698252B2
公开(公告)日：2014-04-15
申请号：US13456939
申请日：2012-04-26
申请人： Po-Nien Chen , Jin-Aun Ng , Ming Zhu , Bao-Ru Young , Hak-Lay Chuang
发明人： Po-Nien Chen , Jin-Aun Ng , Ming Zhu , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L27/11
CPC分类号： H01L21/823842 , H01L21/28158 , H01L21/823857 , H01L27/0629 , H01L28/20 , H01L29/0653 , H01L29/4933 , H01L29/511 , H01L29/512 , H01L29/517 , H01L29/78
摘要： A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.
摘要翻译：描述了在基板的不同区域上具有五个栅极叠层的半导体器件及其制造方法。该器件包括半导体衬底和用于分离衬底上的不同区域的隔离特征。不同的区域包括p型场效应晶体管（pFET）芯区域，输入/输出pFET（pFET IO）区域，n型场效应晶体管（nFET）核心区域，输入/输出nFET（nFET） IO）区域和高电阻区域。

18. 发明申请

US20140061775A1 SYSTEM AND METHOD FOR A FIELD-EFFECT TRANSISTOR WITH A RAISED DRAIN STRUCTURE 有权
标题翻译：具有提高排水结构的场效应晶体管的系统和方法
公开(公告)号：US20140061775A1
公开(公告)日：2014-03-06
申请号：US13599642
申请日：2012-08-30
申请人： Hak-Lay Chuang , Ming Zhu
发明人： Hak-Lay Chuang , Ming Zhu
IPC分类号： H01L29/78 , H01L27/092 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823418 , H01L21/823431 , H01L21/823828 , H01L21/823885 , H01L27/11273 , H01L29/42392
摘要： A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes forming a frustoconical source by etching a semiconductor substrate, the frustoconical source protruding above a planar surface of the semiconductor substrate; forming a transistor gate, a first portion of the transistor gate surrounding a portion of the frustoconical source and a second portion of the gate configured to couple to a first electrical contact; and forming a drain having a raised portion configured to couple to a second electrical contact and located at a same level above the planar surface of the semiconductor substrate as the second portion of the transistor gate. A semiconductor device having a raised drain structure is also disclosed.
摘要翻译：公开了一种形成具有升高的漏极结构的场效应晶体管的方法。该方法包括：通过蚀刻半导体衬底来形成截头圆锥形源，所述截头圆锥形源突出在所述半导体衬底的平坦表面上方; 形成晶体管栅极，所述晶体管栅极的第一部分围绕所述截头圆锥形源的一部分，并且所述栅极的第二部分被配置为耦合到第一电触头; 以及形成具有凸起部分的漏极，所述凸起部分被配置为耦合到第二电接触并且位于与所述晶体管栅极的第二部分在所述半导体衬底的平面表面上方相同的高度处。还公开了一种具有升高的漏极结构的半导体器件。

19. 发明授权

US08592945B2 Large dimension device and method of manufacturing same in gate last process 有权
标题翻译：大尺寸装置及其制造方法
公开(公告)号：US08592945B2
公开(公告)日：2013-11-26
申请号：US13160096
申请日：2011-06-14
申请人： Hak-Lay Chuang , Ming Zhu
发明人： Hak-Lay Chuang , Ming Zhu
IPC分类号： H01L21/02
CPC分类号： H01L28/60 , H01L21/823437 , H01L29/66181 , H01L29/94
摘要： An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a capacitor having a doped region disposed in a semiconductor substrate, a dielectric layer disposed over the doped region, and an electrode disposed over the dielectric layer. At least one post feature embedded in the electrode.
摘要翻译：公开了一种集成电路器件及其制造方法。在一个示例中，集成电路器件包括具有设置在半导体衬底中的掺杂区域的电容器，设置在掺杂区域上的电介质层和设置在电介质层上的电极。至少有一个帖子功能嵌入电极。

20. 发明授权

US08586436B2 Method of forming a variety of replacement gate types including replacement gate types on a hybrid semiconductor device 有权
标题翻译：在混合半导体器件上形成包括替换栅极类型的各种替换栅极类型的方法
公开(公告)号：US08586436B2
公开(公告)日：2013-11-19
申请号：US13424935
申请日：2012-03-20
申请人： Jin-Aun Ng , Ming Zhu , Chi-Wen Liu
发明人： Jin-Aun Ng , Ming Zhu , Chi-Wen Liu
IPC分类号： H01L21/8234
CPC分类号： H01L21/823864 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66606
摘要： Provided is a method and device that includes providing for a plurality of differently configured gate structures on a substrate. For example, a first gate structure associated with a transistor of a first type and including a first dielectric layer and a first metal layer; a second gate structure associated with a transistor of a second type and including a second dielectric layer, a second metal layer, a polysilicon layer, the second dielectric layer and the first metal layer; and a dummy gate structure including the first dielectric layer and the first metal layer.
摘要翻译：提供了一种方法和装置，其包括在衬底上提供多个不同配置的栅极结构。例如，与第一类型的晶体管相关并包括第一介电层和第一金属层的第一栅极结构; 与第二类型的晶体管相关联并包括第二介电层，第二金属层，多晶硅层，第二介电层和第一金属层的第二栅极结构; 以及包括第一介电层和第一金属层的虚拟栅极结构。

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