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1. 发明申请

US20130126977A1 N/P BOUNDARY EFFECT REDUCTION FOR METAL GATE TRANSISTORS 有权
标题翻译： N / P边界效应减少金属栅极晶体管
公开(公告)号：US20130126977A1
公开(公告)日：2013-05-23
申请号：US13299152
申请日：2011-11-17
申请人： Hak-Lay Chuang , Cheng-Cheng Kuo , Ching-Che Tsai , Ming Zhu , Bao-Ru Young
发明人： Hak-Lay Chuang , Cheng-Cheng Kuo , Ching-Che Tsai , Ming Zhu , Bao-Ru Young
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L27/0207 , H01L21/0274 , H01L21/28123 , H01L21/32139 , H01L21/823456 , H01L27/092 , H01L29/41775 , H01L29/42356 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate. The dummy gates extend along a first axis. The method includes forming a masking layer over the dummy gates. The masking layer defines an elongate opening extending along a second axis different from the first axis. The opening exposes first portions of the dummy gates and protects second portions of the dummy gates. A tip portion of the opening has a width greater than a width of a non-tip portion of the opening. The masking layer is formed using an optical proximity correction (OPC) process. The method includes replacing the first portions of the dummy gates with a plurality of first metal gates. The method includes replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成多个虚拟栅极。虚拟门沿着第一轴延伸。该方法包括在伪栅极上形成掩模层。掩蔽层限定沿着不同于第一轴线的第二轴线延伸的细长开口。开口暴露虚拟门的第一部分并保护虚拟门的第二部分。开口的尖端部分的宽度大于开口的非尖端部分的宽度。使用光学邻近校正（OPC）工艺形成掩模层。该方法包括用多个第一金属栅极替换伪栅极的第一部分。该方法包括用与第一金属栅极不同的多个第二金属栅极替换伪栅极的第二部分。

2. 发明授权

US08703595B2 N/P boundary effect reduction for metal gate transistors 有权
标题翻译：金属栅极晶体管的N / P边界效应降低
公开(公告)号：US08703595B2
公开(公告)日：2014-04-22
申请号：US13299152
申请日：2011-11-17
申请人： Hak-Lay Chuang , Cheng-Cheng Kuo , Ching-Che Tsai , Ming Zhu , Bao-Ru Young
发明人： Hak-Lay Chuang , Cheng-Cheng Kuo , Ching-Che Tsai , Ming Zhu , Bao-Ru Young
IPC分类号： H01L21/336
CPC分类号： H01L27/0207 , H01L21/0274 , H01L21/28123 , H01L21/32139 , H01L21/823456 , H01L27/092 , H01L29/41775 , H01L29/42356 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate. The dummy gates extend along a first axis. The method includes forming a masking layer over the dummy gates. The masking layer defines an elongate opening extending along a second axis different from the first axis. The opening exposes first portions of the dummy gates and protects second portions of the dummy gates. A tip portion of the opening has a width greater than a width of a non-tip portion of the opening. The masking layer is formed using an optical proximity correction (OPC) process. The method includes replacing the first portions of the dummy gates with a plurality of first metal gates. The method includes replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成多个虚拟栅极。虚拟门沿着第一轴延伸。该方法包括在伪栅极上形成掩模层。掩蔽层限定沿着不同于第一轴线的第二轴线延伸的细长开口。开口暴露虚拟门的第一部分并保护虚拟门的第二部分。开口的尖端部分的宽度大于开口的非尖端部分的宽度。使用光学邻近校正（OPC）工艺形成掩模层。该方法包括用多个第一金属栅极替换伪栅极的第一部分。该方法包括用与第一金属栅极不同的多个第二金属栅极替换伪栅极的第二部分。

3. 发明申请

US20130205265A1 OPTICAL PROXIMITY CORRECTION CONVERGENCE CONTROL 有权
标题翻译：光临近度校正综合控制
公开(公告)号：US20130205265A1
公开(公告)日：2013-08-08
申请号：US13368919
申请日：2012-02-08
申请人： Cheng-Cheng Kuo , Ching-Che Tsai , Tzu-Chun Lo , Chih-Wei Hsu , Hua-Tai Lin , Tsai-Sheng Gau , Wen-Chun Huang , Chih-Shiang Chou , Hsin-Chang Lee , Kuei Shun Chen
发明人： Cheng-Cheng Kuo , Ching-Che Tsai , Tzu-Chun Lo , Chih-Wei Hsu , Hua-Tai Lin , Tsai-Sheng Gau , Wen-Chun Huang , Chih-Shiang Chou , Hsin-Chang Lee , Kuei Shun Chen
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F7/70125
摘要： A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.
摘要翻译：一种光学邻近校正（OPC）会聚控制的方法，包括提供具有光掩模和照明器的光刻系统。该方法还包括执行照明器在光掩模上的曝光。此外，该方法包括在第一模板中以第一方向限定的门间距优化光刻系统的光照射器设置。此外，该方法包括确定OPC校正器以使目标边缘放置误差（EPE）收敛OPC结果，以产生第一模板的第一OPC设置。第一个OPC设置针对第一个模板中定义的门间距的相对较小的EPE和掩模误差增强因子（MEEF）。此外，该方法包括在第二相邻模板中检查与相对小的EPE，MEEF和DOM一致性的第一OPC设置与限定的门间距的第一模板。

4. 发明授权

US08656319B2 Optical proximity correction convergence control 有权
标题翻译：光学接近校正收敛控制
公开(公告)号：US08656319B2
公开(公告)日：2014-02-18
申请号：US13368919
申请日：2012-02-08
申请人： Cheng-Cheng Kuo , Ching-Che Tsai , Tzu-Chun Lo , Chih-Wei Hsu , Hua-Tai Lin , Tsai-Sheng Gau , Wen-Chun Huang , Chih-Shiang Chou , Hsin-Chang Lee , Kuei Shun Chen
发明人： Cheng-Cheng Kuo , Ching-Che Tsai , Tzu-Chun Lo , Chih-Wei Hsu , Hua-Tai Lin , Tsai-Sheng Gau , Wen-Chun Huang , Chih-Shiang Chou , Hsin-Chang Lee , Kuei Shun Chen
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F7/70125
摘要： A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.
摘要翻译：一种光学邻近校正（OPC）会聚控制的方法，包括提供具有光掩模和照明器的光刻系统。该方法还包括执行照明器在光掩模上的曝光。此外，该方法包括在第一模板中以第一方向限定的门间距优化光刻系统的光照射器设置。此外，该方法包括确定OPC校正器以使目标边缘放置误差（EPE）收敛OPC结果，以产生第一模板的第一OPC设置。第一个OPC设置针对第一个模板中定义的门间距的相对较小的EPE和掩模误差增强因子（MEEF）。此外，该方法包括在第二相邻模板中检查第一OPC设置以获得相对较小的EPE，MEEF和DOM与限定的门间距的第一模板的一致性。

5. 发明申请

US20120072874A1 DISSECTION SPLITTING WITH OPTICAL PROXIMITY CORRECTION AND MASK RULE CHECK ENFORCEMENT 有权
标题翻译：具有光学接近校正和掩蔽规则检查执行的分离
公开(公告)号：US20120072874A1
公开(公告)日：2012-03-22
申请号：US12884442
申请日：2010-09-17
申请人： Chia-Ping Chiang , Yu-Po Tang , Ming-Hui Chih , Cheng-Kun Tsai , Wei-Long Wang , Wen-Chun Huang , Ru-Gun Liu , Tsai-Sheng Gau , Cheng-Lung Tsai , Josh J.H. Feng , Bing-Syun Yeh , Jeng-Shiun Ho , Cheng-Cheng Kuo
发明人： Chia-Ping Chiang , Yu-Po Tang , Ming-Hui Chih , Cheng-Kun Tsai , Wei-Long Wang , Wen-Chun Huang , Ru-Gun Liu , Tsai-Sheng Gau , Cheng-Lung Tsai , Josh J.H. Feng , Bing-Syun Yeh , Jeng-Shiun Ho , Cheng-Cheng Kuo
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.
摘要翻译：本公开提供了集成电路（IC）设计方法的一个实施例。该方法包括接收具有多个主要特征的IC设计布局; 将主要特征解剖应用于IC设计布局的主要特征，并生成主要特征的子部分; 对主要特征执行光学邻近校正（OPC）; 执行掩模规则检查（MRC）到IC设计布局的主要特征; 并且如果主要特征使MRC故障，则修改主要特征的一个子部分。

6. 发明授权

US07701034B2 Dummy patterns in integrated circuit fabrication 有权
标题翻译：集成电路制造中的虚拟模式
公开(公告)号：US07701034B2
公开(公告)日：2010-04-20
申请号：US11281030
申请日：2005-11-17
申请人： Harry Chuang , Kong-Beng Thei , Cheng-Cheng Kuo
发明人： Harry Chuang , Kong-Beng Thei , Cheng-Cheng Kuo
IPC分类号： H01L27/088
CPC分类号： H01L27/0207 , H01L21/823437 , H01L21/823481 , Y10S438/926
摘要： An embodiment of the invention provides a semiconductor integrated circuit device having a dummy pattern for improving micro-loading effects. The device comprises an active region in a substrate and an isolation region in the substrate adjacent the active region. A plurality of dummy patterns are formed over the isolation region, wherein each dummy pattern is aligned parallel to and lengthwise dimension of the active region. The dummy patterns may have non-uniform spacing or non-uniform aspect ratios. The dummy pattern may have, in plan view, a rectangular shape, wherein its length is greater than the lengthwise dimension of the active region. The spacing between the dummy pattern and the active region may be less than about 1500 nm.
摘要翻译：本发明的实施例提供了一种具有用于改善微负载效应的虚拟图案的半导体集成电路器件。该器件包括衬底中的有源区和邻近有源区的衬底中的隔离区。在隔离区域上形成多个虚拟图案，其中每个虚拟图案与活动区域平行且纵向尺寸排列。假图形可以具有不均匀的间隔或不均匀的纵横比。虚拟图案可以在平面图中具有矩形形状，其长度大于活动区域的纵向尺寸。虚拟图案和有源区域之间的间隔可以小于约1500nm。

7. 发明申请

US20060163665A1 Dummy patterns in integrated circuit fabrication 有权
标题翻译：集成电路制造中的虚拟模式
公开(公告)号：US20060163665A1
公开(公告)日：2006-07-27
申请号：US11281030
申请日：2005-11-17
申请人： Harry Chuang , Kong-Beng Thei , Cheng-Cheng Kuo
发明人： Harry Chuang , Kong-Beng Thei , Cheng-Cheng Kuo
IPC分类号： H01L29/76
CPC分类号： H01L27/0207 , H01L21/823437 , H01L21/823481 , Y10S438/926
摘要： An embodiment of the invention provides a semiconductor integrated circuit device having a dummy pattern for improving micro-loading effects. The device comprises an active region in a substrate and an isolation region in the substrate adjacent the active region. A plurality of dummy patterns are formed over the isolation region, wherein each dummy pattern is aligned parallel to and lengthwise dimension of the active region. The dummy patterns may have non-uniform spacing or non-uniform aspect ratios. The dummy pattern may have, in plan view, a rectangular shape, wherein its length is greater than the lengthwise dimension of the active region. The spacing between the dummy pattern and the active region may be less than about 1500 nm.
摘要翻译：本发明的实施例提供了一种具有用于改善微负载效应的虚拟图案的半导体集成电路器件。该器件包括衬底中的有源区和邻近有源区的衬底中的隔离区。在隔离区域上形成多个虚拟图案，其中每个虚拟图案与活动区域平行且纵向尺寸排列。假图形可以具有不均匀的间隔或不均匀的纵横比。虚拟图案可以在平面图中具有矩形形状，其长度大于活动区域的纵向尺寸。虚拟图案和有源区域之间的间隔可以小于约1500nm。

8. 发明授权

US08765329B2 Sub-resolution rod in the transition region 有权
标题翻译：分解杆在过渡区域
公开(公告)号：US08765329B2
公开(公告)日：2014-07-01
申请号：US12940230
申请日：2010-11-05
申请人： Jeng-Shiun Ho , Luke Lo , Ting-Chun Liu , Min-Hung Cheng , Jing-Wei Shih , Wen-Han Chu , Cheng-Cheng Kuo , Hua-Tai Lin , Tsai-Sheng Gau , Ru-Gun Liu , Yu-Hsiang Lin , Shang-Yu Huang
发明人： Jeng-Shiun Ho , Luke Lo , Ting-Chun Liu , Min-Hung Cheng , Jing-Wei Shih , Wen-Han Chu , Cheng-Cheng Kuo , Hua-Tai Lin , Tsai-Sheng Gau , Ru-Gun Liu , Yu-Hsiang Lin , Shang-Yu Huang
IPC分类号： G03F1/36
CPC分类号： G03F1/36
摘要： The present disclosure provides a photomask. The photomask includes a first integrated circuit (IC) feature formed on a substrate; and a second IC feature formed on the substrate and configured proximate to the first IC feature. The first and second IC features define a dense pattern having a first pattern density. The second IC feature is further extended from the dense pattern, forming an isolated pattern having a second pattern density less than the first pattern density. A transition region is defined from the dense pattern to the isolated pattern. The photomask further includes a sub-resolution rod (SRR) formed on the substrate, disposed in the transition region, and connected with the first IC feature.
摘要翻译：本公开提供了一种光掩模。光掩模包括形成在基板上的第一集成电路（IC）特征; 以及形成在所述基板上并被配置为接近所述第一IC特征的第二IC特征。第一和第二IC特征定义了具有第一图案密度的致密图案。第二IC特征从致密图形进一步扩展，形成具有小于第一图案密度的第二图案密度的隔离图案。从密集图案到隔离图案定义过渡区域。光掩模还包括形成在基板上的分解杆（SRR），其设置在过渡区域中，并与第一IC特征连接。

9. 发明申请

US20070083846A1 Optimized modules' proximity correction 审中-公开
标题翻译：优化模块的接近校正
公开(公告)号：US20070083846A1
公开(公告)日：2007-04-12
申请号：US11192254
申请日：2005-07-28
申请人： Harry Chuang , Cheng-Cheng Kuo
发明人： Harry Chuang , Cheng-Cheng Kuo
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method comprising dissecting a photomask pattern layout into a plurality of segments, each segment having at least one evaluation point, applying a rule-based MPC to the photomask pattern layout and generating a rule-based MPC result, and applying a model-based MPC to the plurality of segments of the photomask pattern layout and generating an MPC correction that is influenced by the rule-based MPC result.
摘要翻译：一种方法，包括将光掩模图案布局解剖成多个段，每个段具有至少一个评估点，将基于规则的MPC应用到光掩模图案布局并生成基于规则的MPC结果，以及应用基于模型的MPC 到光掩模图案布局的多个段，并产生受基于规则的MPC结果影响的MPC校正。

10. 发明授权

US08381153B2 Dissection splitting with optical proximity correction and mask rule check enforcement 有权
标题翻译：用光学邻近校正和掩模规则检查执行的解剖分割
公开(公告)号：US08381153B2
公开(公告)日：2013-02-19
申请号：US12884442
申请日：2010-09-17
申请人： Chia-Ping Chiang , Yu-Po Tang , Ming-Hui Chih , Cheng-Kun Tsai , Wei-Long Wang , Wen-Chun Huang , Ru-Gun Liu , Tsai-Sheng Gau , Cheng-Lung Tsai , Josh J. H. Feng , Bing-Syun Yeh , Jeng-Shiun Ho , Cheng-Cheng Kuo
发明人： Chia-Ping Chiang , Yu-Po Tang , Ming-Hui Chih , Cheng-Kun Tsai , Wei-Long Wang , Wen-Chun Huang , Ru-Gun Liu , Tsai-Sheng Gau , Cheng-Lung Tsai , Josh J. H. Feng , Bing-Syun Yeh , Jeng-Shiun Ho , Cheng-Cheng Kuo
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.
摘要翻译：本公开提供了集成电路（IC）设计方法的一个实施例。该方法包括接收具有多个主要特征的IC设计布局; 将主要特征解剖应用于IC设计布局的主要特征，并生成主要特征的子部分; 对主要特征执行光学邻近校正（OPC）; 执行掩模规则检查（MRC）到IC设计布局的主要特征; 并且如果主要特征使MRC故障，则修改主要特征的一个子部分。

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