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11. 发明申请

US20120131266A1 MEMORY CONTROLLER, DATA STORAGE SYSTEM INCLUDING THE SAME, METHOD OF PROCESSING DATA 审中-公开
标题翻译：存储器控制器，包括其的数据存储系统，处理数据的方法
公开(公告)号：US20120131266A1
公开(公告)日：2012-05-24
申请号：US13301961
申请日：2011-11-22
申请人： Kyoung Lae CHO , Kwang Ho Kim , Jun Jin Kong , Jin Kyu Kim
发明人： Kyoung Lae CHO , Kwang Ho Kim , Jun Jin Kong , Jin Kyu Kim
IPC分类号： G06F12/00
CPC分类号： G06F12/04 , G06F2212/401
摘要： A data storage system includes a controller configured to receive data and data information about the data from a host, analyze the data information, detect whether the data has been compressed, and compress the data according to a detection result; and a nonvolatile memory device configured to store the data compressed by the controller and information about whether the data has been compressed. The controller includes a buffer configured to temporarily store the data and the data information received from the host, an analyzer configured to output, based on an analysis result, a compression control flag that indicates whether the data has been compressed, and a compressor configured to selectively compress or bypass the data based on the compression control flag, and to transmit the data to the nonvolatile memory device.
摘要翻译：数据存储系统包括控制器，被配置为从主机接收关于数据的数据和数据信息，分析数据信息，检测数据是否已被压缩，并根据检测结果压缩数据; 以及非易失性存储装置，被配置为存储由所述控制器压缩的数据以及关于所述数据是否被压缩的信息。所述控制器包括被配置为临时存储从所述主机接收到的数据和数据信息的缓冲器，分析器，被配置为基于分析结果输出指示所述数据是否已被压缩的压缩控制标志，以及压缩器，基于压缩控制标志选择性地压缩或旁路数据，并将数据发送到非易失性存储器件。

12. 发明授权

US07911848B2 Memory device and memory data determination method 有权
标题翻译：存储器和存储器数据确定方法
公开(公告)号：US07911848B2
公开(公告)日：2011-03-22
申请号：US12461060
申请日：2009-07-30
申请人： Heeseok Eun , Jae Hong Kim , Kyoung Lae Cho
发明人： Heeseok Eun , Jae Hong Kim , Kyoung Lae Cho
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5642 , G11C16/3418 , G11C16/3427
摘要： A memory device and a memory data determination method are provided. The memory device may estimate a threshold voltage shift of a first memory cell based on data before the first memory cell is programmed and a target program threshold voltage of the first memory cell. The memory device may generate a metric of a threshold voltage shift of a second memory cell based on the estimated threshold voltage shift of the first memory cell. Also, the memory device may determine data stored in the second memory cell based on the metric.
摘要翻译：提供存储器件和存储器数据确定方法。存储器件可以基于第一存储器单元被编程之前的数据和第一存储器单元的目标程序阈值电压来估计第一存储器单元的阈值电压偏移。存储器件可以基于第一存储器单元的估计的阈值电压偏移来产生第二存储器单元的阈值电压偏移的度量。此外，存储器设备可以基于度量来确定存储在第二存储器单元中的数据。

13. 发明申请

US20110038207A1 FLASH MEMORY DEVICE, PROGRAMMING AND READING METHODS PERFORMED IN THE SAME 有权
标题翻译： FLASH存储器件，编程和读取方法
公开(公告)号：US20110038207A1
公开(公告)日：2011-02-17
申请号：US12856698
申请日：2010-08-16
申请人： Hee-seok Eun , Jong-han Kim , Jae-hong Kim , Dong-hyuk Chae , Seung-hwan Song , Han-woong Yoo , Jun-jin Kong , Young-hwan Lee , Kyoung-lae Cho , Yong-june Kim
发明人： Hee-seok Eun , Jong-han Kim , Jae-hong Kim , Dong-hyuk Chae , Seung-hwan Song , Han-woong Yoo , Jun-jin Kong , Young-hwan Lee , Kyoung-lae Cho , Yong-june Kim
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642
摘要： The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.
摘要翻译：闪存器件包括控制逻辑电路和位电平转换逻辑电路。控制逻辑电路对N位MLC闪速存储器件的存储单元阵列中的第一至第N位数据进行编程，或响应于程序命令和程序命令之一从存储单元阵列中读取数据的第一至第N位读命令。在数据的第一至第N位被完全编程或读取之后，位电平转换控制逻辑电路响应于控制信号编程或读取数据的第（N + 1）位。位电平转换控制逻辑电路转换用于编程或读取数据的第一至第N位的电压电平，以对与第（N + 1）个对应的2N + 1个单元分布的2N个单元分布进行编程或读取）位，然后编程或读取其他2N个单元分布。

14. 发明授权

US07843727B2 Memory device and data reading method 有权
标题翻译：存储器和数据读取方式
公开(公告)号：US07843727B2
公开(公告)日：2010-11-30
申请号：US12232138
申请日：2008-09-11
申请人： Kyoung Lae Cho , Donghun Yu , Yoon Dong Park , Jun Jin Kong , Jae Hong Kim , Heeseok Eun
发明人： Kyoung Lae Cho , Donghun Yu , Yoon Dong Park , Jun Jin Kong , Jae Hong Kim , Heeseok Eun
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/3418 , G11C29/00
摘要： A memory device and a memory data reading method are provided. The memory device may include: a multi-bit cell array; a programming unit that stores N data pages in a memory page in the multi-bit cell array; and a control unit that divides the N data pages into a first group and second group, reads data of the first group from the memory page, and determines a scheme of reading data of the second group from the memory page based on the read data of the first group.
摘要翻译：提供存储器件和存储器数据读取方法。存储器件可以包括：多位单元阵列; 编程单元，其将N个数据页存储在多位单元阵列中的存储器页面中; 以及控制单元，其将N个数据页划分为第一组和第二组，从存储器页面读取第一组的数据，并且基于读取的数据确定从存储器页面读取第二组的数据的方案第一组。

15. 发明授权

US07706181B2 Multi-bit programming device and method using single-bit memory cells 有权
标题翻译：多位编程设备和使用单位存储单元的方法
公开(公告)号：US07706181B2
公开(公告)日：2010-04-27
申请号：US11896349
申请日：2007-08-31
申请人： Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
发明人： Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C2211/5621 , G11C2211/5641
摘要： A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to select backup memory cells in the memory cell array with respect to each bit of the original multi-bit data, and program each bit of the original multi-bit data to a respective one of the selected backup memory cells.
摘要翻译：提供了一种用于非易失性存储器的多位编程设备和方法。在一个示例实施例中，多位编程设备可以包括多位编程单元，其被配置为将原始多位数据多位地编程到存储单元阵列中的目标存储器单元，以及备份编程单元，被配置为选择备份相对于原始多位数据的每个位存储单元阵列中的存储器单元，以及将原始多位数据的每个位编程到所选择的备份存储器单元中的相应一个。

16. 发明申请

US20100091578A1 Nonvolatile Memory Devices Having Built-in Memory Cell Recovery During Block Erase and Methods of Operating Same 有权
标题翻译：在块擦除期间具有内置存储器单元恢复的非易失性存储器件和操作方法相同
公开(公告)号：US20100091578A1
公开(公告)日：2010-04-15
申请号：US12498508
申请日：2009-07-07
申请人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
发明人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/16
摘要： Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.
摘要翻译：非易失性存储器件包括在擦除非易失性（例如闪存）存储器单元块的操作期间的支持存储器单元恢复。非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控制器。存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作，该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元，然后发出使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。

17. 发明申请

US20090296486A1 Memory device and memory programming method 有权
标题翻译：存储器和存储器编程方法
公开(公告)号：US20090296486A1
公开(公告)日：2009-12-03
申请号：US12382351
申请日：2009-03-13
申请人： Jae Hong Kim , Kyoung Lae Cho , Yong June Kim , Dong Hyuk Chae
发明人： Jae Hong Kim , Kyoung Lae Cho , Yong June Kim , Dong Hyuk Chae
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C2211/5621
摘要： Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell.
摘要翻译：提供存储器件和/或存储器编程方法。存储器件可以包括：包括多个存储器单元的存储单元阵列; 编程单元，被配置为将与编程电压相对应的多个脉冲施加到所述多个存储单元中的每一个的栅极端子，并且将编程状态电压施加到与具有低于阈值电压的阈值电压的存储单元连接的位线来自所述多个存储单元中的验证电压; 以及控制单元，被配置为在每个脉冲的第一时间间隔期间增加编程电压的第一增量，并且在第二时间间隔期间增加每个脉冲的第二增量的编程电压。由此，可以减小存储单元的阈值电压分布的宽度。

18. 发明申请

US20090222701A1 Apparatus for determining number of bits to be stored in memory cell 失效
标题翻译：用于确定要存储在存储单元中的位数的装置
公开(公告)号：US20090222701A1
公开(公告)日：2009-09-03
申请号：US12219103
申请日：2008-07-16
申请人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
发明人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
IPC分类号： G06F11/00 , G06F12/16
CPC分类号： G11C11/56 , G06F11/1012 , G11C29/00
摘要： Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell.
摘要翻译：示例性实施例涉及可以确定要存储在存储器单元中的数据的长度的装置，并且可以基于所确定的长度将数据存储在存储器中。根据示例实施例的存储器数据存储装置可以包括：确定单元，其可以确定要存储在存储器单元中的数据的位数和数据检测信息的位数; 数据接收单元，其可以接收与所确定的位数相对应的数据; 纠错编码单元，其可以对所接收的数据执行纠错编码，并生成与数据检测信息的位数相对应的数据检测信息; 以及数据存储单元，其可以将所接收的数据和生成的数据检测信息存储在存储单元中。

19. 发明申请

US20090190396A1 Memory device and method of reading memory data 有权
标题翻译：存储器件和读取存储器数据的方法
公开(公告)号：US20090190396A1
公开(公告)日：2009-07-30
申请号：US12219264
申请日：2008-07-18
申请人： Kyoung Lae Cho , Dong Hun Yu , Jun Jin Kong , Seung-Hwan Song , Yoon Dong Park , Jong Han Kim , Young Hwan Lee
发明人： Kyoung Lae Cho , Dong Hun Yu , Jun Jin Kong , Seung-Hwan Song , Yoon Dong Park , Jong Han Kim , Young Hwan Lee
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/34 , G11C11/5642 , G11C2211/5634
摘要： A memory device and a method of reading multi-bit data stored in a multi-bit cell array may be provided. The memory device may include a multi-bit cell array including a least one memory page with each memory page having a plurality of multi-bit cells, and a determination unit to divide the plurality of multi-bit cells into a first group and second group. The first group may include multi-bit cells with a threshold voltage higher than a reference voltage. The second group may include multi-bit cells with a threshold voltage lower than the reference voltage. The determination unit may sequentially update the first group and second group while changing the reference voltage.
摘要翻译：可以提供存储器件和读取存储在多位单元阵列中的多位数据的方法。存储器件可以包括多比特单元阵列，其包括至少一个存储器页，每个存储器页具有多个多位单元，以及确定单元，用于将多个多位单元划分成第一组和第二组。第一组可以包括具有高于参考电压的阈值电压的多位单元。第二组可以包括阈值电压低于参考电压的多位单元。确定单元可以在改变参考电压的同时顺序地更新第一组和第二组。

20. 发明申请

US20090177931A1 Memory device and error control codes decoding method 有权
标题翻译：存储器件和错误控制代码解码方法
公开(公告)号：US20090177931A1
公开(公告)日：2009-07-09
申请号：US12153121
申请日：2008-05-14
申请人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
发明人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： G06F11/141 , G06F11/1012 , G06F11/1072 , G11C11/5642 , G11C16/10 , G11C29/00
摘要： Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.
摘要翻译：可以提供存储器件和/或错误控制代码（ECC）解码方法。存储器件可以包括存储单元阵列和解码器，以通过第一读取方案对从存储器单元阵列读取的第一数据进行硬判决解码，并且生成输出数据和输出数据的输出数据和错误信息。存储器装置还可以包括和控制单元，用于基于错误信息确定输出数据的错误率，并且基于错误率来确定是否向存储器单元阵列发送用于软判决解码的附加读命令。可以通过这样的存储器件来减少ECC解码时间。

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