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1. 发明授权

US08339846B2 Flash memory device, programming and reading methods performed in the same 有权
标题翻译： Flash存储器件，编程和读取方法在同一个执行
公开(公告)号：US08339846B2
公开(公告)日：2012-12-25
申请号：US12856698
申请日：2010-08-16
申请人： Hee-seok Eun , Jong-han Kim , Jae-hong Kim , Dong-hyuk Chae , Seung-hwan Song , Han-woong Yoo , Jun-jin Kong , Young-hwan Lee , Kyoung-lae Cho , Yong-june Kim
发明人： Hee-seok Eun , Jong-han Kim , Jae-hong Kim , Dong-hyuk Chae , Seung-hwan Song , Han-woong Yoo , Jun-jin Kong , Young-hwan Lee , Kyoung-lae Cho , Yong-june Kim
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642
摘要： The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.
摘要翻译：闪存器件包括控制逻辑电路和位电平转换逻辑电路。控制逻辑电路对N位MLC闪速存储器件的存储单元阵列中的第一至第N位数据进行编程，或响应于程序命令和程序命令之一从存储单元阵列中读取数据的第一至第N位读命令。在数据的第一至第N位被完全编程或读取之后，位电平转换控制逻辑电路响应于控制信号编程或读取数据的第（N + 1）位。位电平转换控制逻辑电路转换用于编程或读取数据的第一至第N位的电压电平，以对与第（N + 1）个对应的2N + 1个单元分布的2N个单元分布进行编程或读取）位，然后编程或读取其他2N个单元分布。

2. 发明申请

US20110038207A1 FLASH MEMORY DEVICE, PROGRAMMING AND READING METHODS PERFORMED IN THE SAME 有权
标题翻译： FLASH存储器件，编程和读取方法
公开(公告)号：US20110038207A1
公开(公告)日：2011-02-17
申请号：US12856698
申请日：2010-08-16
申请人： Hee-seok Eun , Jong-han Kim , Jae-hong Kim , Dong-hyuk Chae , Seung-hwan Song , Han-woong Yoo , Jun-jin Kong , Young-hwan Lee , Kyoung-lae Cho , Yong-june Kim
发明人： Hee-seok Eun , Jong-han Kim , Jae-hong Kim , Dong-hyuk Chae , Seung-hwan Song , Han-woong Yoo , Jun-jin Kong , Young-hwan Lee , Kyoung-lae Cho , Yong-june Kim
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642
摘要： The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.
摘要翻译：闪存器件包括控制逻辑电路和位电平转换逻辑电路。控制逻辑电路对N位MLC闪速存储器件的存储单元阵列中的第一至第N位数据进行编程，或响应于程序命令和程序命令之一从存储单元阵列中读取数据的第一至第N位读命令。在数据的第一至第N位被完全编程或读取之后，位电平转换控制逻辑电路响应于控制信号编程或读取数据的第（N + 1）位。位电平转换控制逻辑电路转换用于编程或读取数据的第一至第N位的电压电平，以对与第（N + 1）个对应的2N + 1个单元分布的2N个单元分布进行编程或读取）位，然后编程或读取其他2N个单元分布。

3. 发明授权

US08397116B2 Decoding method and memory system device using the same 有权
标题翻译：解码方法和使用其的内存系统设备
公开(公告)号：US08397116B2
公开(公告)日：2013-03-12
申请号：US12652768
申请日：2010-01-06
申请人： Jong-seon No , Beom-kyu Shin , Ho-sung Park , Yong-june Kim , Jae-hong Kim , Young-hwan Lee , Jun-jin Kong
发明人： Jong-seon No , Beom-kyu Shin , Ho-sung Park , Yong-june Kim , Jae-hong Kim , Young-hwan Lee , Jun-jin Kong
IPC分类号： H03M13/00
CPC分类号： H03M13/1111 , H03M13/1108 , H03M13/3707 , H03M13/451 , H03M13/458 , H04L1/0045 , H04L1/0057
摘要： A decoding method includes performing a first decoding method and performing a second decoding method when decoding of the first decoding method fails. The first decoding method includes updating multiple variable nodes and multiple check nodes using probability values of received data. The second decoding method includes selecting at least one variable node from among the multiple variable nodes; correcting probability values of data received in the selected at least one variable node; updating the variable nodes and the check nodes using the corrected probability values; and determining whether decoding of the second decoding method is successful.
摘要翻译：解码方法包括当解码第一解码方法失败时执行第一解码方法并执行第二解码方法。第一解码方法包括使用接收数据的概率值来更新多个可变节点和多个校验节点。第二解码方法包括从多个可变节点中选择至少一个变量节点; 校正在所选择的至少一个可变节点中接收的数据的概率值; 使用校正的概率值更新变量节点和校验节点; 以及确定所述第二解码方法的解码是否成功。

4. 发明申请

US20100174959A1 DECODING METHOD AND MEMORY SYSTEM DEVICE USING THE SAME 有权
标题翻译：使用该解码方法和存储器系统设备
公开(公告)号：US20100174959A1
公开(公告)日：2010-07-08
申请号：US12652768
申请日：2010-01-06
申请人： Jong-seon No , Beom-kyu Shin , Ho-sung Park , Yong-june Kim , Jae-hong Kim , Young-hwan Lee , Jun-jin Kong
发明人： Jong-seon No , Beom-kyu Shin , Ho-sung Park , Yong-june Kim , Jae-hong Kim , Young-hwan Lee , Jun-jin Kong
IPC分类号： H03M13/03 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/1108 , H03M13/3707 , H03M13/451 , H03M13/458 , H04L1/0045 , H04L1/0057
摘要： A decoding method includes performing a first decoding method and performing a second decoding method when decoding of the first decoding method fails. The first decoding method includes updating multiple variable nodes and multiple check nodes using probability values of received data. The second decoding method includes selecting at least one variable node from among the multiple variable nodes; correcting probability values of data received in the selected at least one variable node; updating the variable nodes and the check nodes using the corrected probability values; and determining whether decoding of the second decoding method is successful.
摘要翻译：解码方法包括当解码第一解码方法失败时执行第一解码方法并执行第二解码方法。第一解码方法包括使用接收数据的概率值来更新多个可变节点和多个校验节点。第二解码方法包括从多个可变节点中选择至少一个变量节点; 校正在所选择的至少一个可变节点中接收的数据的概率值; 使用校正的概率值更新变量节点和校验节点; 以及确定所述第二解码方法的解码是否成功。

5. 发明申请

US20130070526A1 FLASH MEMORY AND READING METHOD OF FLASH MEMORY 有权
标题翻译：闪速存储器的闪存和读取方法
公开(公告)号：US20130070526A1
公开(公告)日：2013-03-21
申请号：US13618336
申请日：2012-09-14
申请人： Hee-seok Eun , Sang-hoon Lee , Jae-hong Kim , Sun-mi Yoo , Seok-min Yoon , Jong-youl Lee
发明人： Hee-seok Eun , Sang-hoon Lee , Jae-hong Kim , Sun-mi Yoo , Seok-min Yoon , Jong-youl Lee
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3436 , G11C16/349
摘要： A reading method of a flash memory, the reading method including: sensing hard data of a first target page by using a first hard read voltage; and generating soft data of the first target page by using at least one pair of, that is, two, first soft read voltages whose voltage levels are different from a voltage level of the first hard read voltage, while the flash memory performs a first operation on the hard data.
摘要翻译：一种闪存的读取方法，所述读取方法包括：通过使用第一硬读取电压来感测第一目标页面的硬数据; 以及通过使用电压电平不同于第一硬读取电压的电压电平的至少一对，即两个第一软读取电压来产生第一目标页面的软数据，而闪存执行第一操作对硬数据。

6. 发明授权

US09001587B2 Flash memory and reading method of flash memory 有权
标题翻译：闪存和闪存的读取方式
公开(公告)号：US09001587B2
公开(公告)日：2015-04-07
申请号：US13618336
申请日：2012-09-14
申请人： Hee-seok Eun , Sang-hoon Lee , Jae-hong Kim , Sun-mi Yoo , Seok-min Yoon , Jong-youl Lee
发明人： Hee-seok Eun , Sang-hoon Lee , Jae-hong Kim , Sun-mi Yoo , Seok-min Yoon , Jong-youl Lee
IPC分类号： G11C16/06 , G11C16/26 , G11C11/56 , G11C16/34
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3436 , G11C16/349
摘要： A reading method of a flash memory, the reading method including: sensing hard data of a first target page by using a first hard read voltage; and generating soft data of the first target page by using at least one pair of, that is, two, first soft read voltages whose voltage levels are different from a voltage level of the first hard read voltage, while the flash memory performs a first operation on the hard data.
摘要翻译：一种闪存的读取方法，所述读取方法包括：通过使用第一硬读取电压来感测第一目标页面的硬数据; 以及通过使用电压电平不同于第一硬读取电压的电压电平的至少一对，即两个第一软读取电压来产生第一目标页面的软数据，而闪存执行第一操作对硬数据。

7. 发明授权

US06820232B2 Device and method for detecting errors in CRC code having reverse ordered parity bits 失效
标题翻译：用于检测具有反向有序奇偶校验位的CRC码中的错误的装置和方法
公开(公告)号：US06820232B2
公开(公告)日：2004-11-16
申请号：US09905995
申请日：2001-07-17
申请人： Jae-hong Kim , Jun-jin Kong , Sung-han Choi
发明人： Jae-hong Kim , Jun-jin Kong , Sung-han Choi
IPC分类号： H03M1300
CPC分类号： H03M13/09
摘要： A device for detecting in a receiver whether any transmission errors have occurred in the received CRC code, in a case that a transmitter transmits the CRC code created by sequencing the parity bits, which are generated using the generator polynomial, in the reverse order and appending them to the message bits. The device comprises a division unit for dividing the message bits by the parity bit generator polynomial to form the remainder, a comparison unit for bitwise comparing the remainder bits with the reverse ordered parity bits, and a decision unit for deciding whether transmission errors have occurred in the CRC code based on the results of the comparison unit. According to the present invention, the transmission errors in the received CRC code are effectively detected, when the CRC code includes the parity bits sequenced in the reverse order, unlike the conventional normal order.
摘要翻译：在接收到的CRC码中检测出发送错误是否发生的发送装置，在发送方通过使用生成多项式生成的奇偶校验位进行排序创建的CRC码的情况下，以相反的顺序进行检测，并附加他们到消息位。该装置包括：分割单元，用于将消息比特除以奇偶校验位生成多项式以形成余数;比较单元，用于将余数比特与反向有序奇偶校验比特进行比较;以及判定单元，用于判定是否发生了传输错误基于比较单元结果的CRC码。根据本发明，与传统的正常顺序不同，当CRC码包括以相反顺序排列的奇偶校验位时，有效地检测出接收的CRC码中的传输错误。

8. 发明授权

US09477410B2 Memory system and method of operating the memory system 有权
标题翻译：内存系统和操作内存系统的方法
公开(公告)号：US09477410B2
公开(公告)日：2016-10-25
申请号：US14686483
申请日：2015-04-14
申请人： Jae-hong Kim
发明人： Jae-hong Kim
IPC分类号： G06F3/06
CPC分类号： G06F3/0611 , G06F3/0625 , G06F3/0659 , G06F3/0688 , G06F12/00 , G06F13/00 , G11C8/08 , G11C11/5642 , G11C16/08 , G11C16/26
摘要： According to example embodiments, a memory system includes a memory device and a memory controller configured to control the memory device. The memory device includes a plurality of memory cells. The memory controller includes a storage unit configured to sequentially store a plurality of commands received from a host, a distance determination unit configured to determine a distance between a program command and a read command, associated with the same word line, from among the plurality of commands stored in the storage unit, and a read voltage determination unit configured to determine a read voltage level corresponding to the read command based on the determined distance.
摘要翻译：根据示例实施例，存储器系统包括存储器设备和被配置为控制存储器设备的存储器控制器。存储装置包括多个存储单元。所述存储器控制器包括：存储单元，被配置为顺序地存储从主机接收的多个命令;距离确定单元，被配置为确定与所述多个对象相关联的程序命令和与所述相同字线相关联的读取命令之间的距离存储在存储单元中的命令，以及读取电压确定单元，被配置为基于所确定的距离来确定与读取命令相对应的读取电压电平。

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