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11. 发明授权

US06284574B1 Method of producing heat dissipating structure for semiconductor devices 失效
标题翻译：制造半导体器件散热结构的方法
公开(公告)号：US06284574B1
公开(公告)日：2001-09-04
申请号：US09223979
申请日：1999-01-04
申请人： Kevin Shawn Petrarca , Sarah Knickerbocker , Joyce C. Liu , Rebecca D. Mih
发明人： Kevin Shawn Petrarca , Sarah Knickerbocker , Joyce C. Liu , Rebecca D. Mih
IPC分类号： H01L2148
CPC分类号： H01L23/36 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
摘要： A structure and process are described for facilitating the conduction of heat away from a semiconductor device. Thermally conductive planes and columns are incorporated within the back-end structure and around the interconnect outside the chip. A thermally conductive plane is formed by forming a first insulating layer on an underlying layer of the device; forming a recess in the insulating layer; filling the recess with a thermally conductive material to form a lateral heat-dissipating layer; planarizing the heat-dissipating layer to make the top surface thereof coplanar with the unrecessed portion of the insulating layer; and forming a second insulating layer on the first insulating layer and the heat-dissipating layer, thereby embedding the heat-dissipating layer between the first and second insulating layers. The heat-dissipating layer is electrically isolated from the underlying layer of the device, and preferably is electrically grounded.
摘要翻译：描述了用于促进远离半导体器件的热传导的结构和工艺。导热平面和列结合在后端结构中并且围绕芯片外的互连。导热平面通过在器件的下层上形成第一绝缘层而形成; 在所述绝缘层中形成凹部; 用导热材料填充凹部以形成横向散热层; 使散热层平坦化，使其顶面与绝缘层的未加工部分共面; 以及在所述第一绝缘层和所述散热层上形成第二绝缘层，从而将所述散热层嵌入所述第一绝缘层和所述第二绝缘层之间。散热层与器件的下层电隔离，优选电接地。

12. 发明授权

US07833893B2 Method for forming conductive structures 有权
标题翻译：形成导电结构的方法
公开(公告)号：US07833893B2
公开(公告)日：2010-11-16
申请号：US11775257
申请日：2007-07-10
申请人： Stephan Grunow , Kaushik A. Kumar , Kevin Shawn Petrarca , Richard Paul Volant
发明人： Stephan Grunow , Kaushik A. Kumar , Kevin Shawn Petrarca , Richard Paul Volant
IPC分类号： H01L21/44
CPC分类号： H01L21/76873 , H01L21/31144 , H01L21/32139 , H01L21/76865
摘要： A method of forming a method a conductive wire. The method includes forming a dielectric hardmask layer on a dielectric layer; forming an electrically conductive hardmask layer on the dielectric hardmask layer; forming a trench extending through the conductive and dielectric hardmask layers into the dielectric layer; depositing a liner/seed layer on the conductive hardmask layer and the sidewalls and bottom of the trench; filling the trench with a fill material; removing the liner/seed layer from the top surface of the conductive hardmask layer; removing the fill material from the trench; electroplating a metal layer onto exposed surfaces of the conductive hardmask layer and liner/seed layer; and removing the metal layer and the conductive hardmask layer from the dielectric hardmask layer so the metal layer and edges of the liner/seed layer are coplanar with the top surface of the dielectric hardmask layer.
摘要翻译：形成导线方法的方法。该方法包括在电介质层上形成电介质硬掩模层; 在介电硬掩模层上形成导电硬掩模层; 形成延伸穿过所述导电和介电硬掩模层的沟槽进入所述电介质层; 在导电硬掩模层和沟槽的侧壁和底部上沉积衬里/籽晶层; 用填充材料填充沟槽; 从所述导电硬掩模层的顶表面去除所述衬里/籽晶层; 从沟槽中移除填充材料; 将金属层电镀到导电硬掩模层和衬里/籽晶层的暴露表面上; 并且从电介质硬掩模层去除金属层和导电硬掩模层，使得金属层和衬里/籽晶层的边缘与电介质硬掩模层的顶表面共面。

13. 发明授权

US07825019B2 Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits 有权
标题翻译：减小半导体集成电路中寄生电容的结构和方法
公开(公告)号：US07825019B2
公开(公告)日：2010-11-02
申请号：US11863724
申请日：2007-09-28
申请人： Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin Shawn Petrarca , Vidhya Ramachandran
发明人： Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin Shawn Petrarca , Vidhya Ramachandran
IPC分类号： H01L21/44
CPC分类号： H01L23/5222 , H01L21/7682 , H01L21/76829 , H01L23/522 , H01L23/53295 , H01L2924/0002 , Y10S438/926 , Y10S438/928 , H01L2924/00
摘要： A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.
摘要翻译：半导体结构及其形成方法。该结构包括（a）包括半导体器件的衬底和（b）在衬底顶部上的第一ILD（层间电介质）层。该结构还包括第一ILD层中的N个第一实际金属线，N是正整数。 N个第一实际金属线电连接到半导体器件。该结构还包括第一ILD层中的第一沟槽。第一条沟没有完全填满固体材料。如果第一沟槽被完全填充第一虚拟金属线，则（i）第一虚设金属线不与任何半导体器件电连接，并且（ii）N个第一实际金属线和第一虚拟金属线提供基本均匀的跨越第一ILD层的金属线的图案密度。

14. 发明申请

US20090017616A1 METHOD FOR FORMING CONDUCTIVE STRUCTURES 有权
标题翻译：形成导电结构的方法
公开(公告)号：US20090017616A1
公开(公告)日：2009-01-15
申请号：US11775257
申请日：2007-07-10
申请人： Stephan Grunow , Kaushik A. Kumar , Kevin Shawn Petrarca , Richard Paul Volant
发明人： Stephan Grunow , Kaushik A. Kumar , Kevin Shawn Petrarca , Richard Paul Volant
IPC分类号： H01L21/44
CPC分类号： H01L21/76873 , H01L21/31144 , H01L21/32139 , H01L21/76865
摘要： A method of forming a method a conductive wire. The method includes forming a dielectric hardmask layer on a dielectric layer; forming an electrically conductive hardmask layer on the dielectric hardmask layer; forming a trench extending through the conductive and dielectric hardmask layers into the dielectric layer; depositing a liner/seed layer on the conductive hardmask layer and the sidewalls and bottom of the trench; filling the trench with a fill material; removing the liner/seed layer from the top surface of the conductive hardmask layer; removing the fill material from the trench; electroplating a metal layer onto exposed surfaces of the conductive hardmask layer and liner/seed layer; and removing the metal layer and the conductive hardmask layer from the dielectric hardmask layer so the metal layer and edges of the liner/seed layer are coplanar with the top surface of the dielectric hardmask layer.
摘要翻译：形成导线方法的方法。该方法包括在电介质层上形成电介质硬掩模层; 在介电硬掩模层上形成导电硬掩模层; 形成延伸穿过所述导电和介电硬掩模层的沟槽进入所述电介质层; 在导电硬掩模层和沟槽的侧壁和底部上沉积衬里/籽晶层; 用填充材料填充沟槽; 从所述导电硬掩模层的顶表面去除所述衬里/籽晶层; 从沟槽中移除填充材料; 将金属层电镀到导电硬掩模层和衬里/籽晶层的暴露表面上; 并且从电介质硬掩模层去除金属层和导电硬掩模层，使得金属层和衬里/籽晶层的边缘与电介质硬掩模层的顶表面共面。

15. 发明授权

US06864578B2 Internally reinforced bond pads 有权
公开(公告)号：US06864578B2
公开(公告)日：2005-03-08
申请号：US10249381
申请日：2003-04-03
申请人： David Angell , Frederic Beaulieu , Takashi Hisada , Adreanne Kelly , Samuel Roy McKnight , Hiromitsu Miyai , Kevin Shawn Petrarca , Wolfgang Sauter , Richard Paul Volant , Caitlin W. Weinstein
发明人： David Angell , Frederic Beaulieu , Takashi Hisada , Adreanne Kelly , Samuel Roy McKnight , Hiromitsu Miyai , Kevin Shawn Petrarca , Wolfgang Sauter , Richard Paul Volant , Caitlin W. Weinstein
IPC分类号： H01L23/485 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/05073 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/45144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/3025 , H01L2924/04941 , H01L2924/00014 , H01L2924/00
摘要： Disclosed is a reinforced bond pad structure having nonplanar dielectric structures and a metallic bond layer conformally formed over the nonplanar dielectric structures. The nonplanar dielectric structures are substantially reproduced in the metallic bond layer so as to form nonplanar metallic structures. Surrounding each of the nonplanar metallic structures is a ring of dielectric material which provides a hard stop during probing of the bond pad so as to limit the amount of bond pad that can be removed during probing.

16. 发明授权

US06661098B2 High density area array solder microjoining interconnect structure and fabrication method 有权
标题翻译：高密度区阵列焊料微接合互连结构及制造方法
公开(公告)号：US06661098B2
公开(公告)日：2003-12-09
申请号：US10052620
申请日：2002-01-18
申请人： John Harold Magerlein , Kevin Shawn Petrarca , Sampath Purushothaman , Carlos Juan Sambucetti , Richard Paul Volant , George Frederick Walker
发明人： John Harold Magerlein , Kevin Shawn Petrarca , Sampath Purushothaman , Carlos Juan Sambucetti , Richard Paul Volant , George Frederick Walker
IPC分类号： H01L2348
CPC分类号： H01L24/10 , H01L21/67144 , H01L23/49811 , H01L24/13 , H01L2224/05001 , H01L2224/05023 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/0102 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01046 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/30105 , H05K1/0306 , H05K1/112 , H05K3/34 , H05K3/3436 , H05K3/388 , H05K2201/0317 , H05K2201/09472 , H05K2201/09509 , H01L2924/00
摘要： A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.
摘要翻译：教导了通过布置在互连载体上的一组微接点互连一组器件芯片的系统。载体具有致密阵列的具有粘附层，阻挡层和贵金属层的微接点插座; 制造器件晶片的阵列包括粘附层，阻挡层和易熔焊料层的微接合焊盘阵列，焊盘位于相对于屏障插座的匹配位置; 所述器件芯片通过微接点阵列连接到所述载体，导致能够实现非常高的输入/输出密度和芯片间布线密度的互连。

17. 发明申请

US20110109405A1 Low Temperature BI-CMOS Compatible Process For MEMS RF Resonators and Filters 失效
标题翻译：用于MEMS射频谐振器和滤波器的低温BI-CMOS兼容工艺
公开(公告)号：US20110109405A1
公开(公告)日：2011-05-12
申请号：US13007130
申请日：2011-01-14
申请人： Leena Paivikki Buchwalter , Kevin Kok Chan , Timothy Joseph Dalton , Christopher Vincent Jahnes , Jennifer Louise Lund , Kevin Shawn Petrarca , James Louis Speidell , James Francis Ziegler
发明人： Leena Paivikki Buchwalter , Kevin Kok Chan , Timothy Joseph Dalton , Christopher Vincent Jahnes , Jennifer Louise Lund , Kevin Shawn Petrarca , James Louis Speidell , James Francis Ziegler
IPC分类号： H03H9/24
CPC分类号： B81C1/00246 , B81B2201/0271 , B81C1/0023 , B81C2203/0735 , H03H3/0072 , H03H9/2405
摘要： A microelectromechanical system (MEMS) resonator or filter including a first conductive layer, one or more electrodes patterned in the first conductive layer which serve the function of signal input, signal output, or DC biasing, or some combination of these functions, an evacuated cavity, a resonating member comprised of a lower conductive layer and an upper structural layer, a first air gap between the resonating member and one or more of the electrodes, an upper membrane covering the cavity, and a second air gap between the resonating member and the upper membrane.
摘要翻译：一种微机电系统（MEMS）谐振器或滤波器，其包括第一导电层，在第一导电层中图案化的一个或多个电极，其用于信号输入，信号输出或DC偏置的功能，或这些功能的某些组合;抽真空腔，由下导电层和上结构层构成的谐振构件，在谐振构件和一个或多个电极之间的第一气隙，覆盖空腔的上膜，以及谐振构件和第二气隙之间的第二气隙上膜。

18. 发明授权

US07855137B2 Method of making a sidewall-protected metallic pillar on a semiconductor substrate 有权
标题翻译：在半导体衬底上制造侧壁保护的金属柱的方法
公开(公告)号：US07855137B2
公开(公告)日：2010-12-21
申请号：US12190173
申请日：2008-08-12
申请人： Mukta G. Farooq , Waldemar Walter Kocon , Kevin Shawn Petrarca , Richard Paul Volant
发明人： Mukta G. Farooq , Waldemar Walter Kocon , Kevin Shawn Petrarca , Richard Paul Volant
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L24/11 , H01L21/76852 , H01L21/76885 , H01L24/13 , H01L2224/05001 , H01L2224/05023 , H01L2224/05573 , H01L2224/05647 , H01L2224/11002 , H01L2224/11462 , H01L2224/1147 , H01L2224/1184 , H01L2224/13083 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13565 , H01L2224/1357 , H01L2224/13655 , H01L2224/13657 , H01L2224/13671 , H01L2224/13673 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/01015 , H01L2224/13099 , H01L2924/00 , H01L2224/05099
摘要： A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars are free of the protective plating so that the conductive pillars can be readily joined to the pads of a packaging substrate. Also disclosed is a sidewall-protected conductive pillar having a protective coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP thereon.
摘要翻译：在半导体晶片上形成导电柱的方法，其中导电柱镀有Ni，Co，Cr，Rh，NiP，NiB，CoWP或CoP的保护涂层。只有导电柱的一面被电镀。导电柱的端部没有保护电镀，使得导电柱可以容易地接合到封装基板的焊盘。还公开了一种侧壁保护的导电柱，其上具有Ni，Co，Cr，Rh，NiP，NiB，CoWP或CoP的保护涂层。

19. 发明申请

US20090085210A1 STRUCTURES AND METHODS FOR REDUCTION OF PARASITIC CAPACITANCES IN SEMICONDUCTOR INTEGRATED CIRCUITS 有权
标题翻译：半导体集成电路中降低PARASIIC电容的结构与方法
公开(公告)号：US20090085210A1
公开(公告)日：2009-04-02
申请号：US11863724
申请日：2007-09-28
申请人： Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin Shawn Petrarca , Vidhya Ramachandran
发明人： Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin Shawn Petrarca , Vidhya Ramachandran
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L21/76829 , H01L23/522 , H01L23/53295 , H01L2924/0002 , Y10S438/926 , Y10S438/928 , H01L2924/00
摘要： A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.
摘要翻译：半导体结构及其形成方法。该结构包括（a）包括半导体器件的衬底和（b）在衬底顶部上的第一ILD（层间电介质）层。该结构还包括第一ILD层中的N个第一实际金属线，N是正整数。 N个第一实际金属线电连接到半导体器件。该结构还包括第一ILD层中的第一沟槽。第一条沟没有完全填满固体材料。如果第一沟槽被完全填充第一虚拟金属线，则（i）第一虚设金属线不与任何半导体器件电连接，并且（ii）N个第一实际金属线和第一虚拟金属线提供基本均匀的跨越第一ILD层的金属线的图案密度。

20. 发明授权

US06819000B2 High density area array solder microjoining interconnect structure and fabrication method 有权
标题翻译：高密度区阵列焊料微接合互连结构及制造方法
公开(公告)号：US06819000B2
公开(公告)日：2004-11-16
申请号：US10692065
申请日：2003-10-23
申请人： John Harold Magerlein , Kevin Shawn Petrarca , Sampath Purushothaman , Carlos Juan Sambucetti , Richard Paul Volant , George Frederick Walker
发明人： John Harold Magerlein , Kevin Shawn Petrarca , Sampath Purushothaman , Carlos Juan Sambucetti , Richard Paul Volant , George Frederick Walker
IPC分类号： H01L2348
CPC分类号： H01L24/10 , H01L21/67144 , H01L23/49811 , H01L24/13 , H01L2224/05001 , H01L2224/05023 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/0102 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01046 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/30105 , H05K1/0306 , H05K1/112 , H05K3/34 , H05K3/3436 , H05K3/388 , H05K2201/0317 , H05K2201/09472 , H05K2201/09509 , H01L2924/00
摘要： A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; the device chips are joined to the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.
摘要翻译：教导了通过布置在互连载体上的一组微接点互连一组器件芯片的系统。载体具有致密阵列的具有粘附层，阻挡层和贵金属层的微接点插座; 制造器件晶片采用微连接焊盘阵列，其包括粘附层，阻挡层和易熔焊料层，焊盘位于相对于阻挡插座的匹配位置; 器件芯片通过微接点阵列连接到载体，导致能够具有非常高的输入/输出密度和芯片间布线密度的互连。

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