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11. 发明授权

US07795983B1 Chaotic signal enabled low probability intercept communication 有权
标题翻译：混沌信号启用低概率拦截通信
公开(公告)号：US07795983B1
公开(公告)日：2010-09-14
申请号：US11646176
申请日：2006-12-26
申请人： Michael J. Delaney , Jose M. Cruz-Albrecht , Joseph F. Jensen , Keh-Chung Wang
发明人： Michael J. Delaney , Jose M. Cruz-Albrecht , Joseph F. Jensen , Keh-Chung Wang
IPC分类号： H03B29/00
CPC分类号： H03B29/00
摘要： A circuit for generating chaotic signals implemented using heterojunction bipolar transistors (HBTs) and utilized in low probability intercept communications. The HBT chaotic circuit generates truly random analog signals in the GHz range that are non-repeating and deterministic and may not be replicated by preloading a predetermined sequence. A fully differential autonomous chaotic circuit outputs two pairs of chaotic signals to be used in a communication system. As it is impossible to generate identical chaotic signals at the transmitter and receiver sites, the receiver itself sends the chaotic signal to be used for encoding to the transmitter. The receiver includes a chaotic signal generator and digitizes, upconverts, and transmits the generated chaotic signal to the transmitter. The transmitter uses the received chaotic signal to code data to be transmitted. The receiver decodes the transmitted data that is encoded by the chaotic signal to retrieve the transmitted data.
摘要翻译：用于产生使用异质结双极晶体管（HBT）实现并用于低概率截取通信的混沌信号的电路。 HBT混沌电路在GHz范围内产生非重复和确定性的真实随机模拟信号，并且可能不会通过预加载预定序列来复制。全差分自主混沌电路输出要在通信系统中使用的两对混沌信号。由于在发射机和接收站点不可能产生相同的混沌信号，所以接收机本身将发送混沌信号用于编码。接收机包括混沌信号发生器，数字化，上变频，并将发生的混沌信号发送到发射机。发射机使用接收到的混沌信号来编码要传输的数据。接收机对由混沌信号编码的发送数据进行解码以检索发送的数据。

12. 发明申请

US20090141815A1 TIME-ENCODING-BASED HIGH-CAPACITY DIGITAL COMMUNICATION LINK 失效
标题翻译：基于时间编码的高容量数字通信链路
公开(公告)号：US20090141815A1
公开(公告)日：2009-06-04
申请号：US11946844
申请日：2007-11-29
申请人： Peter Petre , Jose Cruz-Albrecht , Joseph F. Jensen
发明人： Peter Petre , Jose Cruz-Albrecht , Joseph F. Jensen
IPC分类号： H04B14/04
CPC分类号： H04B14/026
摘要： The present invention relates to a digital communication architecture based upon the concept of time encoding. In one aspect, systems provide time-encoding-based digital communication, the systems comprising a transmitter, a communication channel, and a receiver. In another aspect, methods for digital communication comprise time encoding digital input data and then transmitting the resultant asynchronous pulse signal to a receiver that converts the asynchronous pulse signal back into digital symbols. Methods of providing a digital communication link can include (i) providing digital symbols, (ii) time encoding the digital symbols to generate asynchronous pulse signals, (iii) communicating switching times of the signals to a receiver, and (iv) digitizing in parallel and reconstructing the digital symbols. The methods and systems of the invention can utilize existing chip-scale circuit technologies and can be characterized by link capacities of 50 Gbit/sec, 100 Gbit/sec, 200 Gbit/sec, or higher.
摘要翻译：本发明涉及一种基于时间编码概念的数字通信体系结构。在一个方面，系统提供基于时间编码的数字通信，所述系统包括发射机，通信信道和接收机。在另一方面，用于数字通信的方法包括对数字输入数据进行时间编码，然后将合成的异步脉冲信号发送到将异步脉冲信号转换回数字符号的接收机。提供数字通信链路的方法可以包括（i）提供数字符号，（ii）对数字符号进行时间编码以产生异步脉冲信号，（iii）将信号的切换时间传送到接收机，以及（iv）并行数字化并重建数字符号。本发明的方法和系统可以利用现有的芯片级电路技术，其特点可以是50Gbit / s，100Gbit / sec，200Gbit / sec或更高的链路容量。

13. 发明授权

US07196649B2 Reprogrammable distributed reference ladder for analog-to-digital converters 有权
标题翻译：用于模数转换器的可编程分布式参考梯形图
公开(公告)号：US07196649B2
公开(公告)日：2007-03-27
申请号：US10772113
申请日：2004-02-03
申请人： Mehran Mokhtari , Joseph F. Jensen
发明人： Mehran Mokhtari , Joseph F. Jensen
IPC分类号： H03M1/12
CPC分类号： H03M1/1057 , H03M1/361
摘要： An analog to digital converter comprises a plurality of comparators, each comparator for comparing an input electrical signal with a respective, pre-selected reference electrical signal, an encoder coupled to the comparators to receive a detection signal from each comparator indicative of the input signal, and a plurality of reference circuits, each reference circuit coupled to a respective one of the plurality of comparators to supply the respective reference electrical signal to the respective comparator.
摘要翻译：模数转换器包括多个比较器，每个比较器用于将输入电信号与相应的预先选择的参考电信号进行比较;耦合到比较器的编码器，用于接收来自指示输入信号的每个比较器的检测信号，以及多个参考电路，每个参考电路耦合到所述多个比较器中的相应一个比较器，以将相应的参考电信号提供给相应的比较器。

14. 发明授权

US5859605A Digital waveform generator and method for synthesizing periodic analog waveforms using table readout of simulated .DELTA.- .SIGMA. analog-to-digital conversion data 失效
标题翻译：数字波形发生器和用于使用模拟DELTA-SIGMA模数转换数据的表读出来合成周期性模拟波形的方法
公开(公告)号：US5859605A
公开(公告)日：1999-01-12
申请号：US789176
申请日：1997-01-24
申请人： Gopal Raghavan , Joseph F. Jensen
发明人： Gopal Raghavan , Joseph F. Jensen
IPC分类号： G06F1/03 , G06J1/00 , H03M3/00
CPC分类号： G06J1/00 , G06F1/0321
摘要： A digital waveform generator reads out simulated .DELTA..SIGMA. ADC data for a desired periodic analog waveform from a memory and converts it, using a low-resolution high speed DAC, into a synthesized analog waveform. The .DELTA..SIGMA. digital waveform generator is preferably designed to take advantage of the natural evolution of device technologies. The memory is fabricated with older technologies, which tend to be slower but have a much higher integration. The DAC is implemented in more recent technologies, which are faster but have less integration. A speed up buffer or buffers in intermediate speed intermediate integration technologies may be included to provide a bridge between the low speed memory and the low integration DAC. As the current technologies become more well developed, and thus more integrated, and new higher speed technologies take their place, the technologies for the various components will gradually change, but the architecture should remain viable and superior to the known digital generators.
摘要翻译：数字波形发生器从存储器读出所需周期性模拟波形的模拟DELTA SIGMA ADC数据，并使用低分辨率高速DAC将其转换为合成的模拟波形。 DELTA SIGMA数字波形发生器最好设计成利用器件技术的自然演进。记忆是用较老的技术制造的，这些技术往往会变慢，但是集成度要高得多。 DAC在更新的技术中实现，这些技术更快，但集成度更低。可以包括加速缓冲器或中速集成技术中的缓冲器，以在低速存储器和低积分DAC之间提供桥接。随着当前技术的发展越来越成熟，新一代的高速技术得到发挥，各种部件的技术将逐渐发生变化，但架构应该保持可行性，而且比已知的数字发电机更优越。

15. 发明授权

US5729230A Delta-Sigma .DELTA.-.SIGMA. modulator having a dynamically tunable continuous time Gm-C architecture 失效
标题翻译：具有动态可调连续时间Gm-C架构的Delta-Sigma DELTA-SIGMA调制器
公开(公告)号：US5729230A
公开(公告)日：1998-03-17
申请号：US588666
申请日：1996-01-17
申请人： Joseph F. Jensen , Gopal Raghavan , Albert E. Cosand
发明人： Joseph F. Jensen , Gopal Raghavan , Albert E. Cosand
IPC分类号： H03M3/02 , H03M3/00
CPC分类号： H03M3/396 , H03M3/406 , H03M3/43 , H03M3/454
摘要： A continuous-time tunable Gm-C architecture for a .DELTA..SIGMA. modulator includes a tunable resonator and a low bit rate, high sample rate quantizer connected in a feedback loop. The resonator shapes the quantization noise spectrum so that the bulk of the quantization noise occurs outside the signal spectrum. A tunable Gm cell tunes the resonator's resonant frequency to maximize the modulator's SNR. The tunable Gm cell includes a fixed Gm cell having transconductance G.sub.f, a current divider and a recombination circuit that together effectively multiply G.sub.f by a factor .alpha., where -1
摘要翻译：用于DELTA SIGMA调制器的连续可调Gm-C架构包括可调谐谐振器和连接在反馈回路中的低比特率高采样率量化器。谐振器对量化噪声谱进行整形，使得量化噪声的大部分发生在信号谱外。可调谐Gm单元调谐谐振器的谐振频率以最大化调制器的SNR。可调谐Gm单元包括具有跨导Gf的固定Gm单元，分流器和复合电路，其一起有效地将Gf乘以因子α，其中-1 <=α<= 1，而不影响单元的共模电流Icm。正电流源提供Icm，同时保持R / 2的共模电阻和理论上无限差分模式电阻。因此，谐振器的谐振频率可以从DC变化到约1Ghz，同时保持稳定的共模工作点并改善调制器的品质因数。

16. 发明授权

US5726600A NPN bipolar circuit topology for a tunable transconductance cell and positive current source 失效
标题翻译：用于可调谐跨导电池和正电流源的NPN双极电路拓扑
公开(公告)号：US5726600A
公开(公告)日：1998-03-10
申请号：US588665
申请日：1996-01-17
申请人： Gopal Raghavan , Joseph F. Jensen , Albert E. Cosand
发明人： Gopal Raghavan , Joseph F. Jensen , Albert E. Cosand
IPC分类号： H03H11/04 , H03F3/45 , H03K5/22
CPC分类号： H03H11/0472 , H03H11/0444
摘要： An active filter circuit component includes an all NPN bipolar tunable Gm cell and a positive current source (PCS) for supplying common mode current. The tunable Gm cell includes a fixed Gm cell having transconductance G.sub.f, a current divider and recombination circuit that together effectively multiply G.sub.f by a tuning factor .alpha., where -1.ltoreq..alpha..ltoreq.1, without effecting the cell's common mode current I.sub.cm. The PCS includes a pair of unity gain inverting single ended amplifiers that are connected in antiparallel across a pair of matched resistors. Alternately, the resistors can be connected across the inverting and non-inverting sides of a differential amplifier. A constant voltage is applied across the resistors to supply I.sub.cm, while maintaining a common mode resistance of R/2 and a differential mode resistance approaching infinity.
摘要翻译：有源滤波器电路组件包括用于提供共模电流的全NPN双极可调谐Gm单元和正电流源（PCS）。可调谐Gm单元包括具有跨导Gf的固定Gm单元，电流分配器和复合电路，其一起有效地将Gf乘以调谐因子α，其中-1 <=α<1，而不影响单元的共模电流Icm 。 PCS包括一对在一对匹配电阻器上反并联连接的单位增益反相单端放大器。或者，电阻器可以跨差分放大器的反相和非反相侧连接。在电阻之间施加恒定电压以提供Icm，同时保持R / 2的共模电阻和接近无限远的差模电阻。

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