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11. 发明授权

US06984874B2 Semiconductor device with metal fill by treatment of mobility layers including forming a refractory metal nitride using TMEDT 失效
$Semiconductor device with metal fill by treatment of mobility layers including forming a refractory metal nitride using TMEDT$
标题翻译：通过处理迁移率层的金属填充的半导体器件，包括使用TMEDT形成难熔金属氮化物
公开(公告)号：US06984874B2
公开(公告)日：2006-01-10
申请号：US10915131
申请日：2004-08-10
申请人： John H. Givens , Russell C. Zahorik , Brenda D. Kraus
发明人： John H. Givens , Russell C. Zahorik , Brenda D. Kraus
IPC分类号： H01L29/40 , H01L23/48 , H01L23/52
CPC分类号： H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A recess having a height-to-width aspect ratio from about 6:1 to about 10:1 in a semiconductor structure is disclosed with a method of forming the same. In a first embodiment, a refractory metal layer is formed in the recess, which can be a trench, a contact hole, or a combination thereof. A refractory metal nitride layer is then formed on the refractory metal layer. A heat treatment is used to form a metal silicide contact at the bottom of the contact hole upon a semiconductor material. In a first alternative method, an ammonia high-temperature treatment is conducted to remove undesirable impurities within the refractory metal nitride layer lining the contact hole and to replace the impurities with more nitrogen. In a second alternative method, a second refractory metal nitride layer is formed by PVD upon the first refractory metal nitride layer. In either alternative, a metallization layer is deposited within the recess.
摘要翻译：通过形成半导体结构的方法，公开了半导体结构中的高度 - 宽度纵横比为约6:1至约10:1的凹槽。在第一实施例中，难熔金属层形成在凹槽中，其可以是沟槽，接触孔或其组合。然后在难熔金属层上形成难熔金属氮化物层。使用热处理在半导体材料上的接触孔的底部形成金属硅化物接触。在第一替代方法中，进行氨高温处理以除去在接触孔内衬的难熔金属氮化物层内的不期望的杂质，并用更多的氮替代杂质。在第二替代方法中，通过PVD在第一难熔金属氮化物层上形成第二难熔金属氮化物层。在任一替代方案中，在凹陷内沉积金属化层。

12. 发明授权

US06787472B2 Utilization of disappearing silicon hard mask for fabrication of semiconductor structures 失效
标题翻译：消耗硅硬掩模的利用用于制造半导体结构
公开(公告)号：US06787472B2
公开(公告)日：2004-09-07
申请号：US10352464
申请日：2003-01-27
申请人： John H. Givens , Mark E. Jost
发明人： John H. Givens , Mark E. Jost
IPC分类号： H01L21302
CPC分类号： H01L27/10882 , H01L21/28518 , H01L21/31144 , H01L21/76802 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10888
摘要： A method of forming structures in semiconductor devices through a buffer or insulator layer comprises the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. This allows for a thinner layer of resist material to be used. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by chemical mechanical planarization.
摘要翻译：通过缓冲层或绝缘体层在半导体器件中形成结构的方法包括在蚀刻结构的图案化抗蚀剂层和下面的阻挡层之间使用硅硬掩模。硅硬掩模用作对抗蚀剂层的支撑，防止如果第一抗蚀剂层在用于蚀刻的开口的蚀刻期间被消除，则通过作为蚀刻停止来防止被抗蚀剂层保护的势垒层的潜在蚀刻结构。这允许使用更薄的抗蚀剂材料层。在蚀刻之后，在硅硬掩模上沉积一层可硅化材料，并将所得结构退火以将硅硬掩模转变为硅化物材料。通过研磨方法例如通过化学机械平面化除去硅化物材料。

13. 发明授权

US06787447B2 Semiconductor processing methods of forming integrated circuitry 有权
标题翻译：形成集成电路的半导体处理方法
公开(公告)号：US06787447B2
公开(公告)日：2004-09-07
申请号：US09952897
申请日：2001-09-11
申请人： John H. Givens
发明人： John H. Givens
IPC分类号： H01L214763
CPC分类号： H01L21/76807 , H01L23/485 , H01L2221/1036
摘要： Semiconductor processing methods of forming integrated circuitry are described. Embodiments provide a substrate having circuit devices. At least three layers are formed over the substrate and through which electrical connection is to be made with at least two of the circuit devices. The three layers comprise first and second layers having an etch stop layer interposed therebetween. Contact openings are formed through the three layers and a patterned masking layer is formed over the three layers to define a conductive line pattern. Material of an uppermost of the first and second layers is selectively removed, relative to the etch stop layer, to define troughs joined with the contact openings. Conductive material is subsequently formed within the joined troughs and contact openings. In some embodiment, contact openings are formed that have an aspect ratio of no less than about 10:1.
摘要翻译：描述形成集成电路的半导体处理方法。实施例提供具有电路装置的基板。在衬底上形成至少三个层，并且通过其与至少两个电路器件形成电连接。三层包括其间插入有蚀刻停止层的第一层和第二层。通过三层形成接触开口，并且在三层上形成图案化掩模层以限定导电线图案。相对于蚀刻停止层，选择性地去除第一层和第二层的最上层的材料以限定与接触开口接合的槽。随后在接合的槽和接触开口内形成导电材料。在一些实施例中，形成具有不小于约10:1的纵横比的接触开口。

14. 发明授权

US06784550B2 Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication 有权
标题翻译：用于在集成电路制造中改进的CMP工艺的金属合金的热处理
公开(公告)号：US06784550B2
公开(公告)日：2004-08-31
申请号：US09945536
申请日：2001-08-30
申请人： Paul A. Farrar , John H. Givens
发明人： Paul A. Farrar , John H. Givens
IPC分类号： H01L2349
CPC分类号： H01L23/53219 , H01L21/76877 , H01L2924/0002 , H01L2924/00
摘要： A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of metal alloy which contains alloy dopant precipitates, and performing a first anneal of the integrated circuit to drive the alloy dopants into solid solution. The metal is quenched to prevent the alloy dopants from coming out of solution prior to removing excess metal alloy with a polish process. To improve conductivity after polishing, the dopants are allowed to come out of solution. The metal alloy is described as aluminum with alloy dopants of silicon and copper where the first anneal is performed at 400 to 500° C. This process is particularly applicable to fabrication of interconnects formed using a dual damascene process. The integrated circuit is described as any circuit, but can be a memory device such as a DRAM.
摘要翻译：描述了一种热处理方法，其改进集成电路金属抛光并增加抛光后的导电性。描述了一种在集成电路中制造金属层的方法，其包括以下步骤：沉积包含合金掺杂剂沉淀物的金属合金层，以及执行集成电路的第一退火以将合金掺杂剂驱动为固溶体。在用抛光工艺除去多余的金属合金之前，将金属淬火以防止合金掺杂剂从溶液中脱出。为了提高抛光后的导电性，允许掺杂剂从溶液中脱出。金属合金被描述为具有硅和铜的合金掺杂剂的铝，其中在400-500℃下进行第一次退火。该工艺特别适用于使用双镶嵌工艺形成的互连的制造。集成电路被描述为任何电路，但是可以是诸如DRAM的存储器件。

15. 发明授权

US06689693B2 Methods for utilization of disappearing silicon hard mask for fabrication of semiconductor structures 有权
标题翻译：利用消失的硅硬掩模制造半导体结构的方法
公开(公告)号：US06689693B2
公开(公告)日：2004-02-10
申请号：US10267063
申请日：2002-10-07
申请人： John H. Givens , Mark E. Jost
发明人： John H. Givens , Mark E. Jost
IPC分类号： H01L21302
CPC分类号： H01L27/10882 , H01L21/28518 , H01L21/31144 , H01L21/76802 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10888
摘要： A method of forming structures in semiconductor devices through a buffer or insulator layer comprises the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by CMP.
摘要翻译：通过缓冲层或绝缘体层在半导体器件中形成结构的方法包括在蚀刻结构的图案化抗蚀剂层和下面的阻挡层之间使用硅硬掩模。硅硬掩模用作对抗蚀剂层的支撑，防止如果第一抗蚀剂层在用于蚀刻的开口的蚀刻期间被消除，则通过作为蚀刻停止来防止被抗蚀剂层保护的势垒层的潜在蚀刻结构。在蚀刻之后，在硅硬掩模上沉积一层可硅化材料，并将所得结构退火以将硅硬掩模转变为硅化物材料。通过研磨方法，例如通过CMP去除硅化物材料。

16. 发明授权

US06404053B2 Utilization of energy absorbing layer to improve metal flow and fill in a novel interconnect structure 失效
标题翻译：利用能量吸收层改善金属流动并填充新的互连结构
公开(公告)号：US06404053B2
公开(公告)日：2002-06-11
申请号：US09282385
申请日：1999-03-31
申请人： John H. Givens
发明人： John H. Givens
IPC分类号： H01L2348
CPC分类号： H01L21/76882 , H01L23/5226 , H01L23/53223 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for manufacturing an interconnect structure situated on a semiconductor wafer having a substrate assembly thereon. The interconnect structure is formed in a recess such as a trench, a hole, a via, or a combination of a trench and a hole or via within a dielectric material situated on the substrate assembly of the semiconductor wafer. At least one barrier layer is deposited within the recess. A seed layer helping to promote nucleation, deposition, and growth of a material that will be used to fill up the recess is then deposited on the barrier layer. An electrically conductive layer is then formed upon the seed layer. An energy absorbing layer will then be formed upon the conductor layer, where the energy absorbing layer has a greater thermal absorption capacity than that of the electrically conductive layer. The energy absorbing layer is heated, with or without an applied heightened pressure, to cause the conductor layer to flow so as to fill voids that have formed within the dielectric structure. Following the steps of heating or heating and pressurizing the energy absorbing layer, both the energy absorbing layer and a portion of the conductive layer situated above the dielectric structure are removed.
摘要翻译：公开了一种用于制造位于其上具有基板组件的半导体晶片上的互连结构的方法。互连结构形成在诸如沟槽，孔，通孔的凹槽中，或者位于半导体晶片的衬底组件上的电介质材料内的沟槽和孔或通孔的组合。至少一个阻挡层沉积在凹槽内。有助于促进将用于填充凹部的材料的成核，沉积和生长的种子层然后沉积在阻挡层上。然后在种子层上形成导电层。然后在导体层上形成能量吸收层，其中能量吸收层具有比导电层更大的热吸收能力。在施加或不施加加压的情况下加热能量吸收层，以使导体层流动，从而填充在电介质结构内形成的空隙。在加热或加热能量吸收层的步骤之后，消除能量吸收层和位于电介质结构上方的导电层的一部分。

17. 发明授权

US6060385A Method of making an interconnect structure 失效
标题翻译：制造互连结构的方法
公开(公告)号：US6060385A
公开(公告)日：2000-05-09
申请号：US801819
申请日：1997-02-14
申请人： John H. Givens
发明人： John H. Givens
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/311
CPC分类号： H01L23/522 , H01L21/76807 , H01L21/76838 , H01L21/76877 , H01L23/53219 , H01L23/53223 , H01L2924/0002 , Y10S438/952
摘要： The present invention comprises a metallization method that forms a three-level interconnect in an electrical circuit. The method comprises providing a substrate assembly and depositing thereon a first dielectric layer thereover. A second dielectric layer is then deposited over the first dielectric layer. The second dielectric layer is patterned and anisotropically etched to form contact corridors. The second dielectric layer is again patterned and etched to form trenches, some of which are immediately above the contact corridors. An electrically conductive material is deposited to fill the contact corridors and trenches, and to leave a portion of the electrically conductive material above the second dielectric layer and directly above both the contact corridors and the trenches. The deposition forms a unitary three-level interconnect having a contiguous trench below a contact corridor below a metal line, where the metal line is above the second dielectric layer. An optional antireflective coating can be deposited to assist in filling the trenches and contact corridor. Finally, patterning and etching of the electrically conductive material above the second dielectric layer forms metal lines for the electrical circuit.
摘要翻译：本发明包括在电路中形成三电平互连的金属化方法。该方法包括提供衬底组件并在其上沉积第一介电层。然后在第一介电层上沉积第二电介质层。将第二电介质层图案化并各向异性蚀刻以形成接触走廊。再次对第二介电层进行图案化和蚀刻以形成沟槽，其中一些位于接触走廊的正上方。沉积导电材料以填充接触走廊和沟槽，并且将导电材料的一部分留在第二介电层上方并且直接在接触走廊和沟槽上方。沉积形成一个单一的三电平互连，在金属线下面的接触走廊下方具有连续的沟槽，金属线在第二电介质层之上。可以沉积可选的抗反射涂层以帮助填充沟槽和接触走廊。最后，在第二介电层之上的导电材料的图案化和蚀刻形成用于电路的金属线。

18. 发明授权

US5888896A Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component 失效
公开(公告)号：US5888896A
公开(公告)日：1999-03-30
申请号：US670490
申请日：1996-06-27
申请人： John H. Givens
发明人： John H. Givens
IPC分类号： H01L21/027 , H01L21/285 , H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/31111 , H01L21/0274 , H01L21/28512 , H01L21/76807 , H01L2221/1026 , H01L2221/1036
摘要： An electrical contact and method for making an electrical contact to a node location is disclosed and which includes forming a substrate having a node location to which electrical connection is to be made; forming a first patterned layer of a photosensitive material over the node location; forming a first dielectric layer over the first patterned layer of photosensitive material; planarizing the first dielectric layer to expose at least a portion of the first patterned layer of photosensitive material; forming a second patterned layer of a photosensitive material over the exposed first patterned layer of photosensitive material and the first dielectric layer; forming a second dielectric layer over the second patterned layer of photosensitive material; planarizing the second dielectric layer to expose at least a portion of the second patterned layer of photosensitive material; after planarizing the second dielectric layer, removing the first and second patterned layers of photosensitive material, the removal of the first and second layers of photosensitive material forming a void to the underlying node locations; and filling the void with electrically conductive material to make electrical contact to the node location.

19. 发明授权

US5835987A Reduced RC delay between adjacent substrate wiring lines 失效
公开(公告)号：US5835987A
公开(公告)日：1998-11-10
申请号：US723263
申请日：1996-09-30
申请人： John H. Givens
发明人： John H. Givens
IPC分类号： H01L21/764 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L29/00 , H01L23/58
CPC分类号： H01L23/5222 , H01L21/764 , H01L21/76801 , H01L21/7682 , H01L21/76835 , H01L21/76837 , H01L23/5283 , H01L23/5329 , H01L2924/0002
摘要： A void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. For one approach, hollow silicon spheres define the void. The spheres are fabricated to a known inner diameter, wall thickness and outer diameter. The spheres are rigid enough to withstand the mechanical processes occurring during semiconductor fabrication. The spheres withstand elevated temperatures up to a prescribed temperature range. At or above a desired temperature, the sphere walls disintegrate leaving the void in place. For an alternative approach, adjacent wiring lines are "T-topped" (i.e., viewed cross-sectionally). Dielectric fill is deposited in the spacing between lines. As the dielectric material accumulates on the line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off an internal void.

20. 外观设计

USD269839S Barbecue grill 失效
公开(公告)号：USD269839S
公开(公告)日：1983-07-26
申请号：US331122
申请日：1981-12-16
申请人： John H. Givens, III
设计人： John H. Givens, III

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