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11. 发明授权

US06187629B1 Method of fabricating a DRAM capacitor 有权
标题翻译：制造DRAM电容器的方法
公开(公告)号：US06187629B1
公开(公告)日：2001-02-13
申请号：US09206109
申请日：1998-12-04
申请人： Jing-Horng Gau , Hsiu-Wen Huang , Jhy-Jyi Sze
发明人： Jing-Horng Gau , Hsiu-Wen Huang , Jhy-Jyi Sze
IPC分类号： H01L218242
CPC分类号： H01L28/84 , H01L21/76804 , H01L27/10852 , H01L28/90
摘要： A method of fabricating a DRAM capacitor. A conductive layer and an amorphous silicon layer are formed on a substrate having a dielectric layer. The amorphous silicon layer and the conductive layer are etched to form a region of a capacitor to expose a portion of the dielectric layer. An opening with a profile having a wider upper portion and a narrower lower portion is formed within the conductive layer, and through the opening, the dielectric layer is then etched through to form a node contact window to expose the substrate. An amorphous silicon spacer is formed on the sidewall of conductive layer of the region of the capacitor and fills the node contact window. A selective HSG-Si, a dielectric layer and a polysilicon layer are formed to achieve the fabrication of the capacitor. The conductive layer, the amorphous silicon layer and the HSG-Si serve as a lower electrode of the capacitor and the polysilicon layer serves as an upper electrode of the capacitor.
摘要翻译：一种制造DRAM电容器的方法。在具有电介质层的基板上形成导电层和非晶硅层。蚀刻非晶硅层和导电层以形成电容器的区域以暴露电介质层的一部分。在导电层内形成具有较宽上部和较窄下部的轮廓的开口，然后通过该开口蚀刻通孔以形成节点接触窗以露出衬底。在电容器区域的导电层的侧壁上形成非晶硅间隔物，并填充节点接触窗口。形成选择性HSG-Si，电介质层和多晶硅层，以实现电容器的制造。导电层，非晶硅层和HSG-Si用作电容器的下电极，多晶硅层用作电容器的上电极。

12. 发明授权

US6040232A Method of manufacturing shallow trench isolation 有权
标题翻译：制造浅沟槽隔离的方法
公开(公告)号：US6040232A
公开(公告)日：2000-03-21
申请号：US236955
申请日：1999-01-25
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76235
摘要： A method is described for manufacturing shallow trench isolation. The method comprises the steps of providing a substrate having a pad oxide layer, a mask layer, a trench penetrating through the mask layer and the pad oxide and into the substrate and a first liner oxide layer in the trench. A portion of the first liner oxide layer is stripped away to expose the bottom corner of the mask layer. A portion of the mask layer is stripped away to expose the top corner of the first oxide layer. The first liner oxide layer is removed to expose the surface of the trench. A second liner oxide layer is formed on the sidewall and the base surface of the trench and the trench is filled with an insulating material to form a shallow trench isolation.
摘要翻译：描述了制造浅沟槽隔离的方法。该方法包括以下步骤：提供具有衬垫氧化物层，掩模层，穿透掩模层的沟槽和衬垫氧化物并进入衬底的衬底以及沟槽中的第一衬里氧化物层的步骤。第一衬里氧化物层的一部分被剥离以暴露掩模层的底角。剥离掩模层的一部分以露出第一氧化物层的顶角。去除第一衬里氧化物层以露出沟槽的表面。第二衬里氧化物层形成在沟槽的侧壁和基底表面上，并且沟槽填充有绝缘材料以形成浅沟槽隔离。

13. 发明授权

US07042326B2 Symmetrical inductor 有权
标题翻译：对称电感
公开(公告)号：US07042326B2
公开(公告)日：2006-05-09
申请号：US10707771
申请日：2004-01-11
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F27/34 , H01F2017/0046
摘要： A symmetrical inductor includes a first metal layer, the first metal layer having a first conductive segment disposed on a first side of a line, and a second conductive segment disposed on a second side of the line, the second conductive segment and the first conductive segment being symmetrical to the line; a second metal layer, the second metal layer having a third conductive segment disposed on the first side of the line, and a fourth conductive segment disposed on the second side of the line, the fourth conductive segment and the third conductive segment being symmetrical to the line; a first contact plug for connecting the first conductive segment with a first end of the third conductive segment; a second contact plug for connecting the first conductive segment with a second end of the third conductive segment; a third contact plug for connecting the second conductive segment with a first end of the fourth conductive segment, the third contact plug and the first contact plug being symmetrical to the line; and a fourth contact plug for connecting the second conductive segment with a second end of the fourth conductive segment, the fourth contact plug and the second contact plug being symmetrical to the line.
摘要翻译：对称电感器包括第一金属层，第一金属层具有设置在线的第一侧上的第一导电段和设置在该线的第二侧上的第二导电段，第二导电段和第一导电段与线对称; 第二金属层，所述第二金属层具有设置在所述线的第一侧上的第三导电段，以及设置在所述线的第二侧上的第四导电段，所述第四导电段和所述第三导电段与线; 第一接触插头，用于将第一导电段与第三导电段的第一端连接; 用于将第一导电段与第三导电段的第二端连接的第二接触插塞; 用于将所述第二导电段与所述第四导电段的第一端连接的第三接触插塞，所述第三接触插塞和所述第一接触插塞与所述线对称; 以及用于将所述第二导电段与所述第四导电段的第二端连接的第四接触插塞，所述第四接触插塞和所述第二接触插塞与所述线对称。

14. 发明授权

US06977198B2 Metal-insulator-metal (MIM) capacitor and fabrication method for making the same 有权
标题翻译：金属绝缘体金属（MIM）电容器及其制造方法
公开(公告)号：US06977198B2
公开(公告)日：2005-12-20
申请号：US10905472
申请日：2005-01-06
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21/02 , H01L21/20 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L23/522 , H01L27/108
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor includes a first metal plate; a first capacitor dielectric layer disposed on the first metal plate and a second metal plate stacked on the first capacitor dielectric layer. The first metal plate, the first capacitor dielectric layer, and the second metal plate constitute a lower capacitor. A second capacitor dielectric layer is disposed on the second metal plate. A third metal plate is stacked on the second capacitor dielectric layer. The second metal plate, the second capacitor dielectric layer, and the third metal plate constitute an upper capacitor. The first metal plate and the third metal plate are electrically connected to a first terminal of the MIM capacitor, while the second metal plate is electrically connected to a second terminal of the MIM capacitor.
摘要翻译：金属绝缘体金属（MIM）电容器包括第一金属板; 设置在第一金属板上的第一电容器介质层和堆叠在第一电容器介电层上的第二金属板。第一金属板，第一电容器电介质层和第二金属板构成下电容器。第二电容器电介质层设置在第二金属板上。第三金属板堆叠在第二电容器介电层上。第二金属板，第二电容器电介质层和第三金属板构成上电容器。第一金属板和第三金属板电连接到MIM电容器的第一端子，而第二金属板电连接到MIM电容器的第二端子。

15. 发明申请

US20050266633A1 Method for fabricating capacitor 审中-公开
标题翻译：制造电容器的方法
公开(公告)号：US20050266633A1
公开(公告)日：2005-12-01
申请号：US10856001
申请日：2004-05-28
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21/02 , H01L21/44 , H01L21/8234 , H01L27/08
CPC分类号： H01L28/91 , H01L27/0805
摘要： A method for fabricating a capacitor is described. A metal layer is formed on a substrate, and then an insulating layer is formed over the substrate covering the metal layer. At least one opening is formed in the insulating layer exposing a portion of the metal layer, and a metal spacer is formed on the sidewall of the opening, wherein the metal spacer and the metal layer together constitute a lower electrode. A dielectric layer is formed on the lower electrode, and then an upper electrode is formed on the dielectric layer.
摘要翻译：描述制造电容器的方法。在基板上形成金属层，然后在覆盖金属层的基板上形成绝缘层。在绝缘层中形成至少一个露出金属层的一部分的开口，并且在开口的侧壁上形成金属间隔物，其中金属间隔物和金属层一起构成下电极。在下电极上形成电介质层，然后在电介质层上形成上电极。

16. 发明授权

US06949440B2 Method of forming a varactor 有权
标题翻译：形成变容二极管的方法
公开(公告)号：US06949440B2
公开(公告)日：2005-09-27
申请号：US10605972
申请日：2003-11-11
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21/20 , H01L21/322 , H01L21/329 , H01L27/06 , H01L27/08 , H01L29/93
CPC分类号： H01L29/66174 , H01L27/0629 , H01L27/0808 , H01L29/93
摘要： A method of forming a varactor includes forming an ion well of a first conductivity type on a substrate and a plurality of isolation structures on the ion well. The isolation structures define at least an active area on the ion well. Following that, ions of the first conductivity type are implanted into the ion well to form a doping region within the active area. A doping layer of a second conductivity type is then formed on the substrate to cover portions of the doping region. A salicide layer is formed on the doping region and the doping layer.
摘要翻译：形成变容二极管的方法包括在衬底上形成第一导电类型的离子阱和在离子阱上形成多个隔离结构。隔离结构至少限定了离子阱上的有效面积。之后，将第一导电类型的离子注入到离子阱中，以在有源区内形成掺杂区。然后在衬底上形成第二导电类型的掺杂层以覆盖掺杂区域的部分。在掺杂区域和掺杂层上形成自对准硅化物层。

17. 发明授权

US06882029B1 Junction varactor with high Q factor and wide tuning range 有权
标题翻译：具有高Q因子和宽调谐范围的结点变容二极管
公开(公告)号：US06882029B1
公开(公告)日：2005-04-19
申请号：US10707221
申请日：2003-11-27
申请人： Jing-Horng Gau , Anchor Chen
发明人： Jing-Horng Gau , Anchor Chen
IPC分类号： H01L27/08 , H01L29/93 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/0811 , H01L27/0808 , H01L29/93
摘要： A PN-junction varactor includes a first ion well of first conductivity type formed on a semiconductor substrate of second conductivity type. A first dummy gate is formed over the first ion well. A first gate dielectric layer is formed between the first dummy gate and the first ion well. A second dummy gate is formed over the first ion well at one side of the first dummy gate. A second gate dielectric layer is formed between the second dummy gate and the first ion well. A first heavily doped region of the second conductivity type is located in the first ion well between the first dummy gate and the second dummy gate. The first heavily doped region of the second conductivity type serving as an anode of the PN-junction varactor. Second heavily doped regions of the first conductivity type located in the first ion well at one side of the first dummy gate that is opposite to the first heavily doped region and at one side of the second dummy gate that is opposite to the first heavily doped region, the second heavily doped regions being electrically connected to each other and serving as a cathode of the PN junction varactor.
摘要翻译： PN结变容二极管包括形成在第二导电类型的半导体衬底上的第一导电类型的第一离子阱。在第一离子阱上形成第一伪栅极。在第一虚拟栅极和第一离子阱之间形成第一栅极介电层。在第一虚拟栅极的一侧上的第一离子阱上形成第二伪栅极。在第二虚拟栅极和第一离子阱之间形成第二栅极电介质层。第二导电类型的第一重掺杂区域位于第一伪栅极和第二虚拟栅极之间的第一离子阱中。第二导电类型的第一重掺杂区域用作PN结变容二极管的阳极。第一导电类型的第二重掺杂区域位于第一伪栅极的与第一重掺杂区域相对的一侧处的第一离子阱中，并且位于与第一重掺杂区域相反的第二伪栅极的一侧，第二重掺杂区彼此电连接并用作PN结变容二极管的阴极。

18. 发明授权

US06440791B1 Self aligned bit-line contact opening and node contact opening fabrication process 有权
标题翻译：自对准位线触点开口和节点接触开口制造工艺
公开(公告)号：US06440791B1
公开(公告)日：2002-08-27
申请号：US09690193
申请日：2000-10-16
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L27/10873 , H01L27/10891
摘要： A self-aligned bit-line contact opening and node contact opening fabrication process having the following features: Etching of the periphery MOS spacer is performed before ion implantation of the periphery MOS source/drain region, using the same photoresist layer as a mask. A self-aligned bit-line (node) contact opening and a periphery gate contact opening, above the periphery MOS gate, are formed simultaneously. The etching of the memory cell MOS spacer is performed after the self-aligned bit-line (node) contact opening has been formed. At the same time, the cap layer above the periphery MOS gate, exposed by the periphery gate contact opening, is etched through.
摘要翻译：具有以下特征的自对准位线接触开口和节点接触开口制造工艺：使用与掩模相同的光致抗蚀剂层，在外围MOS源极/漏极区域的离子注入之前进行外围MOS间隔物的蚀刻。外围MOS栅极上方的自对准位线（节点）接触开口和外围栅极接触开口同时形成。在已经形成自对准位线（节点）接触开口之后执行存储单元MOS间隔物的蚀刻。同时，通过外围栅极接触开口露出的外围MOS栅极上方的覆盖层被蚀刻。

19. 发明授权

US06423641B1 Method of making self-aligned bit-lines 失效
标题翻译：制作自对准位线的方法
公开(公告)号：US06423641B1
公开(公告)日：2002-07-23
申请号：US09664428
申请日：2000-09-18
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L2100
CPC分类号： H01L27/10885 , H01L21/76885 , H01L21/76897 , H01L27/10814 , H01L27/10888
摘要： The present invention provides a method of making self-aligned bit-lines on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a plurality of word-lines located on the silicon substrate and a first dielectric layer that covers each word-line. A plurality of bit-line contacts are formed that are level with the surface of the first dielectric layer. A second dielectric layer is formed on the surface of the semiconductor wafer and a plurality of node contacts are formed in the second and first dielectric layer, which are leveled with the surface of the second dielectric layer. Portions of the second dielectric layer are removed to make the top portion of each node contact higher than the surface of the second dielectric layer. A spacer is formed around this top portion of each node contact. Finally, the top portion of each node contact and the spacer are used as hard masks to form a plurality of bit-lines in the second and first dielectric layers, and a plurality of bit-line contacts contact with every bottom portion of the bit-line.
摘要翻译：本发明提供一种在半导体晶片上制作自对准位线的方法。半导体晶片包括硅衬底，位于硅衬底上的多个字线和覆盖每个字线的第一介电层。形成与第一电介质层的表面平齐的多个位线接触。在半导体晶片的表面上形成第二电介质层，并且在与第二电介质层的表面平齐的第二和第一电介质层中形成多个节点接触。除去第二电介质层的部分，使得每个节点的顶部接触高于第二电介质层的表面。在每个节点接触的顶部周围形成间隔物。最后，将每个节点接触件的顶部和间隔件用作硬掩膜，以在第二和第一电介质层中形成多个位线，并且多个位线触点与位位线的每个底部接触，线。

20. 发明授权

US06255191B1 Method of fabricating an isolation structure in an integrated circuit 失效
标题翻译：在集成电路中制造隔离结构的方法
公开(公告)号：US06255191B1
公开(公告)日：2001-07-03
申请号：US09215599
申请日：1998-12-17
申请人： Jing-Horng Gau , Hsiu-Wen Huang
发明人： Jing-Horng Gau , Hsiu-Wen Huang
IPC分类号： H01L21762
CPC分类号： H01L21/76221 , H01L21/7621
摘要： A semiconductor fabrication method is provided for the fabrication of an isolation structure including a shallow-trench isolation (STI) structure in an integrated circuit. This method is characterized by the increase in the thickness of the adhesive layer over that of the prior art and also in the use of thermal oxidation process to form the STI structure. The thick adhesive layer can thus resist the stress from thermal expansion of the various component layers in the integrated circuit during heat treatment. Moreover, the resulting STI structure is not formed with recessed edge portions since the hydrofluoric (HF) etchant acts on the silicon dioxide plug in the STI structure with substantially the same etching rate as on the adhesive layer. Moreover, this method includes no chemical-mechanical polish (CMP) process, so the problem of scratches on the surface of the silicon dioxide plug as seen in the case of the prior art is avoided.
摘要翻译：提供半导体制造方法用于在集成电路中制造包括浅沟槽隔离（STI）结构的隔离结构。该方法的特征在于粘合剂层的厚度比现有技术的厚度增加，以及使用热氧化工艺形成STI结构。因此，厚的粘合剂层因此可以抵抗在热处理期间集成电路中的各种组分层的热膨胀的应力。此外，由于氢氟化（HF）蚀刻剂以与粘合剂层上基本相同的蚀刻速率作用在STI结构中的二氧化硅塞上，所以形成的STI结构不形成为凹入的边缘部分。此外，该方法不包括化学机械抛光（CMP）工艺，因此避免了在现有技术的情况下在二氧化硅塞的表面上划伤的问题。

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