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1. 发明申请

US20050040470A1 Fabrication of self-aligned bipolar transistor 审中-公开
标题翻译：自对准双极晶体管的制造
公开(公告)号：US20050040470A1
公开(公告)日：2005-02-24
申请号：US10951377
申请日：2004-09-28
申请人： Shu-Ya Chuang , Jing-Horng Gau , Anchor Chen
发明人： Shu-Ya Chuang , Jing-Horng Gau , Anchor Chen
IPC分类号： H01L21/331 , H01L21/00 , H01L21/84 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66242 , H01L29/66318
摘要： A method for fabricating a self-aligned bipolar transistor, wherein a substrate having an epitaxial layer formed thereon as a base is provided. After this, a first dielectric layer, a second dielectric layer are sequentially formed on the epitaxial layer, followed by forming an opening in the second dielectric layer. A conductive spacer is formed on the sidewall of the opening. Using the second dielectric layer and the conductive spacer as a mask, a first dielectric layer in the opening is removed. A conductive layer is then formed in the opening as an emitter, followed by completely removing the second dielectric layer. A doping is conducted on the emitter. Using the emitter and the conductive spacer as a mask, a part of the first dielectric layer is removed. Further using the emitter and the conductive spacer as a mask, another doping is conducted to form a part of the epitaxial layer as a base contact region.
摘要翻译：一种用于制造自对准双极晶体管的方法，其中提供了其上形成有外延层作为基底的基板。之后，在外延层上依次形成第一电介质层，第二电介质层，随后在第二电介质层中形成开口。在开口的侧壁上形成导电间隔物。使用第二电介质层和导电间隔物作为掩模，去除开口中的第一介电层。然后在开口中形成导电层作为发射极，然后完全去除第二电介质层。在发射极上进行掺杂。使用发射极和导电间隔物作为掩模，去除第一介电层的一部分。进一步使用发射极和导电间隔物作为掩模，进行另一掺杂以形成作为基极接触区域的外延层的一部分。

2. 发明申请

US20050017322A1 Variable capactor structure and method of manufacture 有权
标题翻译：可变式压盖机结构及制造方法
公开(公告)号：US20050017322A1
公开(公告)日：2005-01-27
申请号：US10921457
申请日：2004-08-18
申请人： Jing-Horng Gau , Anchor Chen
发明人： Jing-Horng Gau , Anchor Chen
IPC分类号： H01L27/08 , H01L29/00 , H01L21/00
CPC分类号： H01L27/0808
摘要： A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.
摘要翻译：一种可变电容器，包括具有第一类型离子掺杂掩埋层，第一类型离子掺杂阱，第二类型离子掺杂区和其上的导电层的衬底。在衬底内形成第一种类型的离子掺杂阱。第一种类型的离子掺杂阱具有空腔。第一类离子掺杂掩埋层位于第一类离子掺杂阱下的衬底中。连接第一种离子掺杂掩埋层和第一种离子掺杂阱。第二类离子掺杂区位于第一类型离子掺杂阱的空腔的底部。导电层位于第一类型的离子掺杂掩埋层之上并与之连接。

3. 发明授权

US06664201B2 Method of manufacturing anti-reflection layer 有权
公开(公告)号：US06664201B2
公开(公告)日：2003-12-16
申请号：US10010865
申请日：2001-12-05
申请人： Jing-Horng Gau , Shuenn-Jeng Chen
发明人： Jing-Horng Gau , Shuenn-Jeng Chen
IPC分类号： H01L21469
CPC分类号： H01L21/0276 , G03F7/091 , H01L21/3145
摘要： An anti-reflection layer and method of manufacture. A silicon substrate has a conductive layer formed thereon. Plasma-enhanced chemical vapor deposition is performed to form a graded silicon oxynitride layer over the conductive layer. During silicon oxynitride deposition, concentration of one of the reactive gases nitrous oxide is gradually reduced so that the graded silicon oxynitride layer is oxygen-rich near bottom but nitrogen-rich near the top.

4. 发明授权

US6156664A Method of manufacturing liner insulating layer 有权
标题翻译：衬垫绝缘层的制造方法
公开(公告)号：US6156664A
公开(公告)日：2000-12-05
申请号：US267883
申请日：1999-03-11
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21/768 , H01L21/302
CPC分类号： H01L21/76831 , H01L21/76897 , H01L2221/1057
摘要： A method of manufacturing a liner insulating layer for a node contact hole. A substrate having an first insulating layer formed thereon is provided, wherein the first insulating layer has a node contact hole penetrating through the first insulating layer and exposing the substrate. A protective layer is formed on the substrate exposed by the node contact hole. A liner insulating layer is formed on the first insulating layer and in the node contact hole. A second insulating layer is formed on a portion of the liner insulating layer formed on the sidewall of the node contact hole. A portion of the liner insulating layer uncovered by the second insulating layer is removed. The protective layer and the second insulating layer are removed.
摘要翻译：一种用于节点接触孔的衬垫绝缘层的制造方法。提供具有形成在其上的第一绝缘层的基板，其中所述第一绝缘层具有贯穿所述第一绝缘层并暴露所述基板的节点接触孔。在由节点接触孔露出的基板上形成保护层。衬垫绝缘层形成在第一绝缘层和节点接触孔中。在形成在节点接触孔的侧壁上的衬垫绝缘层的一部分上形成第二绝缘层。除去由第二绝缘层未覆盖的衬垫绝缘层的一部分。去除保护层和第二绝缘层。

5. 发明授权

US06949438B2 Method of fabricating a bipolar junction transistor 失效
公开(公告)号：US06949438B2
公开(公告)日：2005-09-27
申请号：US10904595
申请日：2004-11-18
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21/331 , H01L29/732
CPC分类号： H01L29/66287 , H01L29/732
摘要： A substrate with a plurality of isolation structures for defining at least an active area thereon is provided. Ions of a first conductive type are implanted into the substrate to form a doping region in the active area. Following that, a protective layer is formed on the substrate, the protective layer having an opening to expose the doping region. A first doping layer of a second conductive type and a second doping layer of the first conductive type are formed on the doping region, respectively, to complete fabrication of a bipolar junction transistor.

6. 发明授权

US06943399B1 Varactor and differential varactor 有权
标题翻译：变容二极管和微分变容二极管
公开(公告)号：US06943399B1
公开(公告)日：2005-09-13
申请号：US10824266
申请日：2004-04-13
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L27/108
CPC分类号： H01L29/93 , H01L27/0808 , H01L27/0811 , H01L29/423
摘要： A varactor is provided. The varactor includes a second type substrate, two gate structures, a first type doped region and a second type doped region. The two gate structures are disposed over the substrate, and each of the gate structures includes an inter-gate dielectric layer and a gate conductive layer. The first type doped region is disposed in the substrate between the two gate structures. The second type doped region is disposed in the substrate at a side of the two gate structures apart from the first type doped region. The first type doped region is electrically connected to a first electrode, and second type doped region is electrically connected to a second electrode, and the two gate structures are electrically connected to the first electrode or the second electrode.
摘要翻译：提供变容二极管。变容二极管包括第二类型衬底，两个栅极结构，第一类型掺杂区和第二类型掺杂区。两个栅极结构设置在衬底上，并且每个栅极结构包括栅极间介电层和栅极导电层。第一类型掺杂区域设置在两个栅极结构之间的衬底中。第二类型掺杂区域设置在离开第一类型掺杂区域的两个栅极结构的一侧的衬底中。第一类型掺杂区域电连接到第一电极，第二类型掺杂区域电连接到第二电极，并且两个栅极结构电连接到第一电极或第二电极。

7. 发明申请

US20050112837A1 METHOD OF FABRICATING A BIPOLAR JUNCTION TRANSISTOR 失效
标题翻译：制造双极性晶体管的方法
公开(公告)号：US20050112837A1
公开(公告)日：2005-05-26
申请号：US10904595
申请日：2004-11-18
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21/331 , H01L29/732 , H01L21/8222
CPC分类号： H01L29/66287 , H01L29/732
摘要： A substrate with a plurality of isolation structures for defining at least an active area thereon is provided. Ions of a first conductive type are implanted into the substrate to form a doping region in the active area. Following that, a protective layer is formed on the substrate, the protective layer having an opening to expose the doping region. A first doping layer of a second conductive type and a second doping layer of the first conductive type are formed on the doping region, respectively, to complete fabrication of a bipolar junction transistor.
摘要翻译：提供了具有用于限定其上的至少一个有效区域的多个隔离结构的衬底。将第一导电类型的离子注入到衬底中以在有源区域中形成掺杂区域。之后，在衬底上形成保护层，保护层具有露出掺杂区的开口。第一导电类型的第一掺杂层和第一导电类型的第二掺杂层分别形成在掺杂区上，以完成双极结型晶体管的制造。

8. 发明授权

US06545307B2 Structure of a DRAM and a manufacturing process therefor 失效
标题翻译： DRAM的结构及其制造工艺
公开(公告)号：US06545307B2
公开(公告)日：2003-04-08
申请号：US10035276
申请日：2002-01-03
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01K31113
CPC分类号： H01L27/10855 , H01L27/10885 , H01L28/84 , H01L28/90
摘要： A structure of a DRAM and a manufacturing process therefor, suitable for a substrate on which a plurality of word lines and a plurality of source/drain regions on sides of each of these word lines are formed. A plurality of bit line contacts and a plurality of node contacts are formed in electric contact with the source/drain regions. A first patterned insulating layer is formed on the substrate, in which a plurality of openings are formed in the insulating layer to expose the bit line contacts. The substrate is covered with a first conductive layer and a second insulating layer in sequence. The second insulating layer, the first conductive layer and the first insulating layer are patterned in sequence to form a plurality of bit line stacked structures and a plurality of bit lines electrically connecting to the bit contacts, exposing the node contacts. As a result, the bit line stacked structure forms a plurality of trenches and the bit line stacked structure is orthogonal to the word lines. A plurality of spacers are formed on sidewalls of the bit line stacked structure. A plurality of second conductive layers are formed conformal to the surfaces of the trenches. The second conductive layers are patterned to form a plurality of bottom electrodes electrically connected to the node contacts.
摘要翻译：一种DRAM的结构及其制造方法，适用于在其上形成有这些字线的每一侧的多个字线和多个源极/漏极区域的基板。多个位线触点和多个节点触点形成为与源/漏区电接触。第一图案化绝缘层形成在基板上，其中在绝缘层中形成多个开口以露出位线触点。衬底被依次覆盖有第一导电层和第二绝缘层。第二绝缘层，第一导电层和第一绝缘层依次图案化以形成多个位线堆叠结构和电连接到位触点的多个位线，露出节点触点。结果，位线堆叠结构形成多个沟槽，并且位线堆叠结构与字线正交。多个间隔件形成在位线堆叠结构的侧壁上。多个第二导电层形成为与沟槽的表面一致。图案化第二导电层以形成电连接到节点触点的多个底部电极。

9. 发明授权

US06221736B1 Fabrication method for a shallow trench isolation structure 失效
标题翻译：浅沟槽隔离结构的制造方法
公开(公告)号：US06221736B1
公开(公告)日：2001-04-24
申请号：US09457578
申请日：1999-12-09
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method for fabricating a shallow trench isolation structure is described, in which a pad oxide layer, a silicon oxy-nitride layer and the silicon nitride layer are sequentially formed on the substrate. Photolithography and etching are further conducted to form a trench in the substrate. A liner oxide layer is then formed on the exposed substrate surface in the trench, followed by removing portions of the silicon nitride layer and the silicon oxy-nitride layer by wet etching. After this, the trench is filled with an oxide material d the excessive oxide material is removed by using the silicon nitride layer as barrier layer. The remaining silicon nitride layer and the silicon oxy-nitride layer are further removed to complete the fabrication of a shallow trench isolation structure.
摘要翻译：描述了一种用于制造浅沟槽隔离结构的方法，其中衬底氧化物层，氮氧化硅层和氮化硅层依次形成在衬底上。进一步进行光刻和蚀刻以在衬底中形成沟槽。然后在沟槽中的暴露的衬底表面上形成衬里氧化物层，然后通过湿蚀刻去除氮化硅层和氮氧化硅层的部分。之后，通过使用氮化硅层作为阻挡层，用氧化物材料d填充过量的氧化物材料。进一步去除剩余的氮化硅层和氮氧化硅层以完成浅沟槽隔离结构的制造。

10. 发明授权

US06204108B1 Method of fabricating a dynamic random access memory capacitor 失效
标题翻译：制造动态随机存取存储器电容器的方法
公开(公告)号：US06204108B1
公开(公告)日：2001-03-20
申请号：US09213783
申请日：1998-12-17
申请人： Jing-Horng Gau , Hsiu-Wen Huang
发明人： Jing-Horng Gau , Hsiu-Wen Huang
IPC分类号： H01L218234
CPC分类号： H01L28/91 , H01L27/10852 , H01L28/84
摘要： A method of fabricating a capacitor. A crown-shape bottom storage node is formed on a conductive region. The crown-shape bottom storage node has a wavelike interior surface and a hemi-spherical grained exterior surface. A dielectric layer is formed on the bottom storage node, and a top electrode is formed to cover the dielectric layer.
摘要翻译：一种制造电容器的方法。在导电区域上形成冠状底部存储节点。冠状底部储存节点具有波浪形内表面和半球形颗粒外表面。在底部存储节点上形成介电层，并且形成顶部电极以覆盖电介质层。

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