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    • 11. 发明授权
    • Bus deadlock avoidance during master split-transactions
    • 主分拆交易期间总线避免避免
    • US5469435A
    • 1995-11-21
    • US187396
    • 1994-01-25
    • William T. KreinRonald R. HochsprungJames D. Kelly
    • William T. KreinRonald R. HochsprungJames D. Kelly
    • G06F13/364G06F13/00
    • G06F13/364
    • Signal transactions are conducted between nodes coupled to a bus, without causing bus deadlock during split transactions. Deadlock avoidance is achieved by rendering a node effectively unavailable at such times to serve as a bus slave for a new bus master. When the "locking" node serves as a transaction source, deadlock is avoided by deasserting, during a split transaction, a buffer-available signal, which is used normally to indicate receiver buffer availability. Additionally, when the "locking" node serves as a transaction destination, deadlock is avoided by deasserting a bus-ownership request signal, which is used normally for requesting bus ownership. After completion of the split transactions, such signals may be unmasked.
    • 信号事务在耦合到总线的节点之间进行,而不会在分离事务期间导致总线死锁。 通过使节点在这样的时间有效地不可用来作为新总线主机的总线从设备来实现死锁避免。 当“锁定”节点用作事务源时,通过在分离事务期间解除缓冲器可用信号来解除死锁,通常用于指示接收器缓冲区可用性。 另外,当“锁定”节点用作事务目的地时,通过解除总线所有权请求信号(通常用于请求总线所有权)来避免死锁。 拆分事务完成后,这些信号可能被屏蔽。
    • 13. 再颁专利
    • Bus transaction reordering in a computer system having unordered slaves
    • 在具有无序奴隶的计算机系统中的总线事务重新排序
    • USRE44688E1
    • 2013-12-31
    • US10669119
    • 2003-09-22
    • James D. KellyMichael L. Regal
    • James D. KellyMichael L. Regal
    • G06F9/46G06F13/36G11C7/00
    • G06F13/362G06F13/16G06F13/1626G06F13/364G06F13/368G06F13/4013
    • A mechanism is provided for reordering Reordering bus transactions to increase increases bus utilization in a computer system in which where a split-transaction bus is bridged to a single-envelope bus. In one embodiment, both masters and slaves are ordered, simplifying implementation. In; in another embodiment, the system is more loosely coupled with only masters being are ordered. Greater bus utilization is thereby achieved. To avoid deadlock, transactions begun on the split-transaction bus are monitored. When a combination of transactions would, result in deadlock if a predetermined further transaction were to begin, result in deadlock, this condition is detected. In the more tightly coupled system, the predetermined further transaction, if it is refused if requested, is refused, thereby avoiding deadlock. In the more loosely-coupled system, the flexibility afforded by unordered slaves is taken advantage of to, in the typical case, reorder the transactions and avoid deadlock without killing any transaction. Where a data dependency exists that would prevent such reordering, the further transactions transaction is killed as in the more tightly-coupled embodiment. Data dependencies are detected in accordance with address-coincidence signals generated by slave devices on a cache-line basis. In accordance with a further optimization, at least one slave device (e.g., DRAM) generates page-coincidence bits. When two transactions to the slave device are to the same address page, the transactions are reordered if necessary to ensure that they are executed one after another without any intervening transaction. Latency of the slave is thereby reduced.
    • 提供了一种机制来重新排序重新排序总线事务以增加在分组事务总线桥接到单信封总线的计算机系统中增加总线利用率。 在一个实施例中,主机和从机都被排序,从而简化了实现。 在; 在另一个实施例中,系统更松散地耦合,只有主人被命令。 从而实现更大的总线利用率。 为了避免死锁,在分割事务总线上开始的事务被监视。 当交易的组合会导致死锁,如果预定的进一步交易开始,则导致死锁,则检测到该条件。 在更紧密耦合的系统中,预定的进一步交易(如果被请求被拒绝)被拒绝,从而避免死锁。 在更松散耦合的系统中,无序奴隶所提供的灵活性被利用于在典型情况下重新排序事务,并避免死锁而不杀死任何事务。 在存在将阻止这种重新排序的数据依赖性的情况下,如更紧密耦合的实施例那样,进一步的事务处理被杀死。 根据从设备在高速缓存行基础上产生的地址一致信号来检测数据依赖性。 根据进一步的优化,至少一个从设备(例如,DRAM)产生寻呼重合位。 当到从设备的两个事务处于相同的地址页面时,如果需要,则事务被重新排序以确保它们被一个接一个执行,而没有任何中间事务。 从而减少从机的延迟。
    • 15. 再颁专利
    • Bus transaction reordering in a computer system having unordered slaves
    • 在具有无序奴隶的计算机系统中的总线事务重新排序
    • USRE38428E1
    • 2004-02-10
    • US10006939
    • 2001-11-30
    • James D. KellyMichael L. Regal
    • James D. KellyMichael L. Regal
    • G06F946
    • G06F13/362G06F13/16G06F13/1626G06F13/364G06F13/368G06F13/4013
    • A mechanism is provided for reordering bus transactions to increase bus utilization in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment, both masters and slaves are ordered, simplifying implementation. In another embodiment, the system is more loosely coupled with only masters being ordered. Greater bus utilization is thereby achieved. To avoid deadlock, transactions begun on the split-transaction bus are monitored. When a combination of transactions would, if a predetermined further transaction were to begin, result in deadlock, this condition is detected. In the more tightly coupled system, the predetermined further transaction, if it is requested, is refused, thereby avoiding deadlock. In the more loosely-coupled system, the flexibility afforded by unordered slaves is taken advantage of to, in the typical case, reorder the transactions and avoid deadlock without killing any transaction. Where a data dependency exists that would prevent such reordering, the further transactions is killed as in the more tightly-coupled embodiment. Data dependencies are detected in accordance with address-coincidence signals generated by slave devices on a cache-line basis. In accordance with a further optimization, at least one slave device (e.g., DRAM) generates page-coincidence bits. When two transactions to the slave device are to the same address page, the transactions are reordered if necessary to ensure that they are executed one after another without any intervening transaction. Latency of the slave is thereby reduced.
    • 19. 发明授权
    • Method and apparatus for serialized interrupt transmission
    • 串行中断传输的方法和装置
    • US5951669A
    • 1999-09-14
    • US773686
    • 1996-12-27
    • Robert L. BaileyLesley A. BirdJames D. Kelly
    • Robert L. BaileyLesley A. BirdJames D. Kelly
    • G06F13/24G06F9/46
    • G06F13/24
    • A computer system in which interrupt signals are serially transmitted from an input/output (I/O) controller is disclosed. The I/O controller initially receives the interrupt signals and then serially transmits them to an interrupt controller where the received interrupt signals are managed. According to the invention, the sequencing by which the interrupt signals are serially transmitted is controlled such that it largely conforms to the sequencing by which the received interrupt signals are processed at the interrupt controller, thereby controlling and reducing latency. The interrupt controller can be a separate integrated circuit chip or integral to another integrated circuit chip of the computer system.
    • 公开了一种从输入/输出(I / O)控制器串行发送中断信号的计算机系统。 I / O控制器最初接收中断信号,然后将它们串行发送到中断控制器,在该中断控制器处理接收到的中断信号。 根据本发明,控制中断信号串行发送的顺序,使其大体上符合中断控制器处理接收到的中断信号的顺序,从而控制和减少等待时间。 中断控制器可以是单独的集成电路芯片或与计算机系统的另一个集成电路芯片集成。
    • 20. 发明授权
    • Deadlock avoidance in a split-bus computer system
    • 分流总线计算机系统中的死锁避免
    • US5933612A
    • 1999-08-03
    • US903412
    • 1997-07-30
    • James D. KellyMichael L. Regal
    • James D. KellyMichael L. Regal
    • G06F13/16G06F13/00
    • G06F13/1626
    • A mechanism is provided for avoiding deadlock in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment, transactions begun on said split-transaction bus are monitored. When a combination of transactions would, if a predetermined further transaction were to begin, result in deadlock, this condition is detected. The predetermined further transaction, if it is requested, is refused, thereby avoiding deadlock. In accordance with another embodiment of the invention, the bus bridge detects when a state of the split-transaction bus would, if a protocol of said split-transaction bus were adhered to, result in deadlock. The bus bridge then drives one or more signals on the split-transaction bus in disregard of the protocol of the split-transaction bus, thereby avoiding deadlock. In accordance with still a further embodiment of the invention, transactions accepted within the bus bridge are monitored. When a combination of said transactions would, if a predetermined further transaction were to begin, result in deadlock, this condition is detected. The predetermined further transaction, if it is requested, is refused, thereby avoiding deadlock.
    • 提供了一种用于避免分组事务总线桥接到单信封总线的计算机系统中的死锁的机制。 在一个实施例中,监视在所述分组交易总线上开始的事务。 当交易的组合将如果预定的进一步交易开始时会导致死锁,则检测到该状况。 如果被请求,预定的另外的事务被拒绝,从而避免死锁。 根据本发明的另一个实施例,如果所述分组交易总线的协议被遵守,则总线桥检测分组交易总线的状态何时会导致死锁。 然后,总线桥驱动分拆事务总线上的一个或多个信号,而不考虑拆分事务总线的协议,从而避免死锁。 根据本发明的又一实施例,监视在总线桥内接受的事务。 当所述交易的组合将如果预定的另外的交易开始时会导致死锁,则检测到该条件。 如果被请求,预定的另外的事务被拒绝,从而避免死锁。