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11. 发明授权

US08373455B1 Output buffer circuit 有权
标题翻译：输出缓冲电路
公开(公告)号：US08373455B1
公开(公告)日：2013-02-12
申请号：US13013725
申请日：2011-01-25
申请人： Alan McLaughlin , Gabriel Li
发明人： Alan McLaughlin , Gabriel Li
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K19/018521
摘要： An output driver circuit can include at least a first driver transistor having a source-drain path coupled between a first power supply node and an output node. A first variable current supply can generate a current having at least one component that is inversely proportional to a power supply voltage. A first driver switch element can be coupled in series with the first variable current supply between a gate of the at least first driver transistor and a second power supply node.
摘要翻译：输出驱动器电路可以包括至少第一驱动器晶体管，其具有耦合在第一电源节点和输出节点之间的源极 - 漏极路径。第一可变电流源可以产生具有与电源电压成反比的至少一个分量的电流。第一驱动器开关元件可以与至少第一驱动器晶体管的栅极和第二电源节点之间的第一可变电流源串联耦合。

12. 发明申请

US20110176647A1 CIRCUIT, SYSTEM AND METHOD FOR MULTIPLEXING SIGNALS WITH REDUCED JITTER 有权
标题翻译：具有减少抖动信号的多路复用信号的电路，系统和方法
公开(公告)号：US20110176647A1
公开(公告)日：2011-07-21
申请号：US13038028
申请日：2011-03-01
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H03D3/24 , H04M9/00 , H04M1/00 , H03K17/16
CPC分类号： H04J3/047 , H03K17/002 , H03K19/1737
摘要： An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.
摘要翻译：一种具有多个电源域和多个逻辑部件的装置。多个逻辑组件中的每一个驻留在多个电源域中的不同的一个中。所述多个逻辑部件中的每一个被配置为与所述多个电源域中的相应一个中的对应的时钟信号一起操作。

13. 发明授权

US07809052B2 Test circuit, system, and method for testing one or more circuit components arranged upon a common printed circuit board 有权
标题翻译：用于测试布置在公共印刷电路板上的一个或多个电路部件的测试电路，系统和方法
公开(公告)号：US07809052B2
公开(公告)日：2010-10-05
申请号：US11460444
申请日：2006-07-27
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H04B3/46
CPC分类号： G01R31/31922 , G01R31/31709 , G01R31/31937
摘要： A test circuit, system, and method are provided herein for testing one or more circuit components arranged upon a monolithic substrate. According to one embodiment, the system may include a test circuit and one or more circuit components, all of which are arranged upon the same monolithic substrate. In general, the test circuit may be configured for: (i) receiving an input signal at an input frequency, (ii) generating a test signal by modulating a phase of the input signal in accordance with a periodic signal, and (iii) supplying either the input signal or the test signal to the one or more integrated circuits, based on a control signal supplied to the test circuit. More specifically, the test circuit may be used to determine the jitter and/or duty cycle distortion (DCD) tolerance of any system component without changing the frequency of the clock signal supplied to the component or injecting noise into the clock recovery system.
摘要翻译：本文提供了测试电路，系统和方法来测试布置在单片基板上的一个或多个电路组件。根据一个实施例，系统可以包括测试电路和一个或多个电路部件，所有电路部件都布置在相同的单片基板上。通常，测试电路可以被配置为：（i）以输入频率接收输入信号，（ii）通过根据周期信号调制输入信号的相位来产生测试信号，以及（iii）提供基于提供给测试电路的控制信号，将输入信号或测试信号传送到一个或多个集成电路。更具体地，测试电路可用于确定任何系统组件的抖动和/或占空比失真（DCD）容限，而不改变提供给组件的时钟信号的频率或将噪声注入到时钟恢复系统中。

14. 发明申请

US20070001720A1 System and method for monitoring a power supply level 有权
标题翻译：监控电源电平的系统和方法
公开(公告)号：US20070001720A1
公开(公告)日：2007-01-04
申请号：US11153773
申请日：2005-06-15
申请人： Gabriel Li , Greg Richmond
发明人： Gabriel Li , Greg Richmond
IPC分类号： H03L7/00
CPC分类号： G06F1/28
摘要： A system and method are provided herein for monitoring the integrity of a power supply by monitoring a level of the power supply voltage supplied to one or more system components. The method, as described herein, includes setting a bit in a status register after the power supply level reaches a threshold level, and monitoring a state of the bit to determine if the power supply level has dropped below the threshold level. For example, the method may determine that the power supply level has dropped below the threshold level if the state of the bit changes from a set bit to a cleared bit. In addition, the system and method described herein may be used for detecting the occurrence of a power abnormality by providing additional resources/information about a power related event.
摘要翻译：本文提供了一种系统和方法，用于通过监视提供给一个或多个系统组件的电源电压的电平来监视电源的完整性。如本文所描述的，该方法包括在电源电平达到阈值电平之后设置状态寄存器中的位，并且监视该位的状态以确定电源电平是否已经降低到阈值电平以下。例如，如果位的状态从设置位改变为清零位，则该方法可以确定电源电平已经降低到阈值电平以下。此外，本文所述的系统和方法可以通过提供关于电力相关事件的附加资源/信息来用于检测电力异常的发生。

15. 发明申请

US20060284655A1 Circuit and method for monitoring the integrity of a power supply 有权
标题翻译：用于监控电源完整性的电路和方法
公开(公告)号：US20060284655A1
公开(公告)日：2006-12-21
申请号：US11153759
申请日：2005-06-15
申请人： Gabriel Li , Greg Richmond
发明人： Gabriel Li , Greg Richmond
IPC分类号： H03L7/00
CPC分类号： G06F1/28 , G01R19/16552
摘要： Circuits and methods are provided herein for monitoring the integrity of a power supply, the circuits and methods providing additional resources/information for diagnosing a cause behind a reset signal, and in some cases, a reason behind a power failure. A first method described herein provides exemplary steps for monitoring a level of a power supply voltage supplied to one or more system components. A second method describes exemplary steps for monitoring an electrical connection between the power supply (or ground supply) and one or more supply pins. Each of the methods involves monitoring a state of one or more bits stored, e.g., within a status register. The methods may be used separately, or in conjunction with one another, for detecting the occurrence of a power abnormality.
摘要翻译：本文提供了用于监测电源的完整性的电路和方法，所述电路和方法提供用于诊断复位信号背后的原因的附加资源/信息，并且在一些情况下是电源故障背后的原因。本文描述的第一种方法提供了用于监测提供给一个或多个系统组件的电源电压的电平的示例性步骤。第二种方法描述了用于监测电源（或接地电源）和一个或多个电源引脚之间的电连接的示例性步骤。每种方法涉及监视存储在例如状态寄存器内的一个或多个位的状态。这些方法可以单独使用，也可以彼此结合使用，用于检测功率异常的发生。

16. 发明授权

US07138841B1 Programmable phase shift and duty cycle correction circuit and method 有权
标题翻译：可编程相移和占空比校正电路及方法
公开(公告)号：US07138841B1
公开(公告)日：2006-11-21
申请号：US11014578
申请日：2004-12-16
申请人： Gabriel Li , Chwei-Po Chew , Dusan Vecera
发明人： Gabriel Li , Chwei-Po Chew , Dusan Vecera
IPC分类号： H03K3/017
CPC分类号： H03K5/151 , H03K5/1565 , H03K2005/00058 , H03K2005/00156
摘要： A phase shift and duty cycle correction circuit is disclosed herein as comprising a programmable digital to analog converter (DAC), a storage device (e.g., a capacitor), a charge sub-circuit and dump sub-circuit for charging and discharging the storage device, respectively, a comparator, and a clock driver circuit. A linearly increasing (or ramped) voltage waveform is generated within the storage device by the charging and discharging actions of the charge and dump sub-circuits; a periodic process which is controlled by opposite phases of the input clock. By programming the DAC control input to change the slicing threshold of the ramped waveform, the circuit and method described herein provides a means for programmable phase shifting and duty cycle correction.
摘要翻译：本文公开了一种相移和占空比校正电路，其包括可编程数模转换器（DAC），存储装置（例如，电容器），用于对存储装置进行充电和放电的充电子电路和转储子电路一个比较器和一个时钟驱动电路。通过充电和转储子电路的充电和放电动作，在存储装置内产生线性增加（或斜坡）的电压波形; 周期性过程由输入时钟的相反相位控制。通过对DAC控制输入进行编程以改变斜坡波形的限幅门限，本文描述的电路和方法提供了可编程相移和占空比校正的方法。

17. 发明授权

US07013359B1 High speed memory interface system and method 有权
标题翻译：高速存储器接口系统及方法
公开(公告)号：US07013359B1
公开(公告)日：2006-03-14
申请号：US10032248
申请日：2001-12-21
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： G06F13/14
CPC分类号： G06F13/4243
摘要： The present invention is a high speed serial memory interface system and method that facilitates efficient communication of information between a system controller operating at a relatively high speed serial communication rate and a memory array operating at a relatively slow speed serial communication rate. In one embodiment the present invention is a high speed serial memory interface system with an information configuration core for coordinating proper alignment of information communication signals, a system interface for communicating with a system controller, and a memory array interface for communicating with a memory array. A memory module array for storing information and a high speed serial memory interface system for providing interface configuration management are integrated on a single substrate.
摘要翻译：本发明是一种高速串行存储器接口系统和方法，其有助于以相对高速的串行通信速率操作的系统控制器与以相对慢的串行通信速率工作的存储器阵列之间的信息的有效通信。在一个实施例中，本发明是具有用于协调信息通信信号的适当对准的信息配置核心的高速串行存储器接口系统，用于与系统控制器通信的系统接口以及用于与存储器阵列通信的存储器阵列接口。用于存储信息的存储器模块阵列和用于提供接口配置管理的高速串行存储器接口系统集成在单个衬底上。

18. 发明授权

US06831346B1 Buried layer substrate isolation in integrated circuits 有权
标题翻译：集成电路中埋地层衬底隔离
公开(公告)号：US06831346B1
公开(公告)日：2004-12-14
申请号：US09849047
申请日：2001-05-04
申请人： Gabriel Li , Kenelm G. D. Murray , Jose Arreola , Shahin Sharifzadeh , K. Nirmal Ratnakumar
发明人： Gabriel Li , Kenelm G. D. Murray , Jose Arreola , Shahin Sharifzadeh , K. Nirmal Ratnakumar
IPC分类号： H01L2900
CPC分类号： H01L29/41758 , H01L21/761 , H01L21/823878 , H01L29/0847
摘要： In an embodiment of an integrated circuit structure having buried layer substrate isolation and a method for forming same, a buried layer having conductivity type opposite to that of an overlying well region is used for wells containing transistors prone to noise generation, where the wells are of the same conductivity type as the substrate. The buried layer may in some embodiments include a first portion underlying the transistor and a second portion spaced apart from and laterally surrounding the first portion. In some embodiments, the circuit may include a doped annular region of the same conductivity type as the buried layer, where the annular region contacts a portion of the buried layer and laterally surrounds the transistor. The circuit may further include metallization adapted to connect the well and annular region to opposite polarities of a power supply voltage, or in some embodiments to preclude such connection.
摘要翻译：在具有掩埋层衬底隔离的集成电路结构及其形成方法的实施例中，具有与上覆阱区相反的导电类型的掩埋层用于容纳产生噪声的晶体管的阱，其中阱为与基片相同的导电类型。在一些实施例中，掩埋层可以包括晶体管下面的第一部分和与第一部分间隔开并横向包围第一部分的第二部分。在一些实施例中，电路可以包括与埋层相同的导电类型的掺杂环形区域，其中环形区域接触掩埋层的一部分并横向围绕晶体管。电路还可以包括适于将阱和环形区域连接到电源电压的相反极性的金属化，或者在一些实施例中以排除这种连接。

19. 发明授权

US06373302B1 Phase alignment system 有权
标题翻译：相位对准系统
公开(公告)号：US06373302B1
公开(公告)日：2002-04-16
申请号：US09533740
申请日：2000-03-23
申请人： Gabriel Li , Paul H. Scott
发明人： Gabriel Li , Paul H. Scott
IPC分类号： H03L700
CPC分类号： H03L7/0814
摘要： An apparatus including a clock circuit and a control circuit. The clock circuit may be configured to generate a first output clock, a second output clock and a first control signal in response to (i) a first input clock, (ii) a second input clock, (iii) a second control signal and (iv) a third control signal. The control circuit may be configured to generate the second control signal and the third control signal in response to the first input clock and the first control signal. The first and second output clocks may have a skew less than a predetermined threshold.
摘要翻译：一种包括时钟电路和控制电路的装置。时钟电路可以被配置为响应于（i）第一输入时钟，（ii）第二输入时钟，（iii）第二控制信号和（iii）第二控制信号而产生第一输出时钟，第二输出时钟和第一控制信号， iv）第三控制信号。控制电路可以被配置为响应于第一输入时钟和第一控制信号而产生第二控制信号和第三控制信号。第一和第二输出时钟可以具有小于预定阈值的偏斜。

20. 发明授权

US06351168B1 Phase alignment system 失效
标题翻译：相位对准系统
公开(公告)号：US06351168B1
公开(公告)日：2002-02-26
申请号：US09533198
申请日：2000-03-23
申请人： Gabriel Li , Paul H. Scott
发明人： Gabriel Li , Paul H. Scott
IPC分类号： H03L700
CPC分类号： G06F1/10 , H03L7/0814
摘要： A circuit including a counter, a state machine and an update circuit. The counter may be configured to present a first control signal and a second control signal in response to a reset signal and a third control signal. The state machine may be configured to generate a select signal in response to (i) the reset signal, (ii) the first control signal and (iii) the second control signal. The update circuit may be configured to generate a fourth control signal in response to the select signal.
摘要翻译：一种包括计数器，状态机和更新电路的电路。计数器可以被配置成响应于复位信号和第三控制信号呈现第一控制信号和第二控制信号。状态机可以被配置为响应于（i）复位信号，（ii）第一控制信号和（iii）第二控制信号而产生选择信号。更新电路可以被配置为响应于选择信号而产生第四控制信号。

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