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11. 发明授权

US06245620B1 Method for foaming MOS transistor having bi-layered spacer 有权
标题翻译：用于发泡具有双层间隔物的MOS晶体管的方法
公开(公告)号：US06245620B1
公开(公告)日：2001-06-12
申请号：US09327459
申请日：1999-06-08
申请人： Keung-hee Jang , Eun-ha Lee
发明人： Keung-hee Jang , Eun-ha Lee
IPC分类号： H01L21331
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28079 , H01L21/28247 , H01L29/6659
摘要： A method is provided for forming a MOS transistor in a highly integrated semiconductor device. In this method a gate pattern is initially formed over a semiconductor substrate. A first dielectric film is then formed over the gate pattern at a first temperature at which deformation or oxidation of a conductive material film forming the gate pattern is prevented. A denser second dielectric film is then formed over the first dielectric film at a second temperature higher than the first temperature. The second and first dielectric film are then anisotropically etched in sequence to form bi-layered spacers on the side walls of the gate pattern, including the first and second dielectric films. Because the deformation of the conductive material film forming the gate pattern is suppressed by forming the first dielectric film at a low temperature, the resistance of the gate electrodes resulting from this fabrication process remains low.
摘要翻译：提供一种用于在高度集成的半导体器件中形成MOS晶体管的方法。在该方法中，最初在半导体衬底上形成栅极图案。然后在形成栅极图案的导电材料膜的变形或氧化被阻止的第一温度下在栅极图案上形成第一电介质膜。然后在高于第一温度的第二温度下在第一介电膜上形成更密集的第二介电膜。然后依次各向异性地蚀刻第二和第一绝缘膜，以在栅极图案的侧壁上形成双层隔离物，包括第一和第二介电膜。由于通过在低温下形成第一电介质膜来抑制形成栅极图案的导电材料膜的变形，所以由该制造工艺产生的栅电极的电阻保持较低。

12. 发明授权

US08574819B2 Method for forming fine pattern 有权
标题翻译：形成精细图案的方法
公开(公告)号：US08574819B2
公开(公告)日：2013-11-05
申请号：US12833833
申请日：2010-07-09
申请人： Sarohan Park , Eun-Ha Lee
发明人： Sarohan Park , Eun-Ha Lee
IPC分类号： G03F7/26
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L27/1052
摘要： A method includes forming a hard mask layer over an etch target layer that extends across first and second regions, forming a sacrificial layer pattern over the hard mask layer of the first region, removing the sacrificial layer pattern after forming a spacer pattern on side walls thereof, selectively etching the hard mask layer of the first region by using the spacer pattern as an etch barrier while protecting the hard mask layer of the second region from being etched, removing the spacer pattern, forming a cut mask pattern over the hard mask layer of the first and second regions, etching the hard mask layer of the first and second regions by using the cut mask pattern as an etch barrier, removing the cut mask pattern, and forming patterns in the first and second regions respectively by using the hard mask layer of the first and second regions as an etch barrier and etching the etch target layer.
摘要翻译：一种方法包括在穿过第一和第二区域延伸的蚀刻目标层上形成硬掩模层，在第一区域的硬掩模层之上形成牺牲层图案，在其侧壁上形成间隔图案之后去除牺牲层图案通过使用间隔图案作为蚀刻屏障来选择性地蚀刻第一区域的硬掩模层，同时保护第二区域的硬掩模层不被蚀刻，去除间隔物图案，在硬掩模层上形成切割掩模图案第一和第二区域，通过使用切割掩模图案作为蚀刻阻挡层来蚀刻第一和第二区域的硬掩模层，去除切割的掩模图案，以及通过使用硬掩模层分别在第一和第二区域中形成图案的第一和第二区域作为蚀刻阻挡层并蚀刻蚀刻目标层。

13. 发明申请

US20120178231A1 METHODS FOR FABRICATING A METAL SILICIDE LAYER AND SEMICONDUCTOR DEVICES USING THE SAME 审中-公开
标题翻译：制造金属硅化物层的方法和使用其的半导体器件
公开(公告)号：US20120178231A1
公开(公告)日：2012-07-12
申请号：US13241678
申请日：2011-09-23
申请人： Jin-Bum Kim , Young-Pil Kim , Hyung-Ik Lee , Ki-Hong Kim , Eun-Ha Lee , Jung-Yun Won , Benayad Anass
发明人： Jin-Bum Kim , Young-Pil Kim , Hyung-Ik Lee , Ki-Hong Kim , Eun-Ha Lee , Jung-Yun Won , Benayad Anass
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/823807 , H01L21/28185 , H01L21/28518 , H01L21/823814 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： Methods for fabricating a metal silicide layer and for fabricating a semiconductor device having such a metal silicide layer are provided wherein, in an embodiment, the method includes the steps of forming a metal layer on a substrate, performing a first thermal process on the substrate to allow the substrate and the metal layer to react with react other to form a first pre-metal silicide layer, removing an unreacted portion of the metal layer, and performing a second thermal process on the substrate to change the first pre-metal silicide layer into a second pre-metal silicide layer and then to melt the second pre-metal silicide layer to change the second pre-metal silicide layer into a metal silicide layer.
摘要翻译：提供了制造金属硅化物层和制造具有这种金属硅化物层的半导体器件的方法，其中在一个实施例中，该方法包括以下步骤：在衬底上形成金属层，在衬底上进行第一热处理，允许衬底和金属层与其它反应物反应以形成第一预金属硅化物层，去除金属层的未反应部分，并在衬底上进行第二热处理以将第一前金属硅化物层改变为第二预金属硅化物层，然后熔化第二预金属硅化物层以将第二预金属硅化物层改变为金属硅化物层。

14. 发明授权

US07995162B2 Liquid crystal display device and method for manufacturing the same 有权
标题翻译：液晶显示装置及其制造方法
公开(公告)号：US07995162B2
公开(公告)日：2011-08-09
申请号：US12318292
申请日：2008-12-24
申请人： Ki Seung Kim , Sang Chul Jung , Jeong Hoon Lee , Dhang Kwon , Hang Sup Cho , Eun Ha Lee , Ho Su Kim
发明人： Ki Seung Kim , Sang Chul Jung , Jeong Hoon Lee , Dhang Kwon , Hang Sup Cho , Eun Ha Lee , Ho Su Kim
IPC分类号： G02F1/1335 , G02F1/1341
CPC分类号： G02F1/136209 , G02F2001/136222
摘要： Disclosed are a liquid crystal display device without a black matrix capable of eliminating light leakage while not decreasing opening degree and reducing production costs and, in addition, a method for fabricating the liquid crystal display device described above. The liquid crystal display device includes: a thin film transistor formed on a first substrate; a first passivation layer formed on the first substrate including the thin film transistor; a color filter layer formed on the first passivation layer; a second passivation layer formed on the first substrate including the color filter layer; a pixel electrode which passes through the second and the first passivation layers, is electrically connected to a part of the thin film transistor and has a lamination structure of transparent metal and opacity metal, wherein the transparent metal part has a width wider than that of the opacity metal part; and a second substrate corresponding to the first substrate.
摘要翻译：公开了一种不具有黑色矩阵的液晶显示装置，并且能够消除漏光，同时不降低开口度并降低生产成本，另外还提供了一种用于制造上述液晶显示装置的方法。液晶显示装置包括：形成在第一基板上的薄膜晶体管; 在包括所述薄膜晶体管的所述第一基板上形成的第一钝化层; 形成在所述第一钝化层上的滤色器层; 形成在包括所述滤色器层的所述第一基板上的第二钝化层; 通过第二钝化层和第一钝化层的像素电极电连接到薄膜晶体管的一部分，并具有透明金属和不透明金属的层叠结构，其中透明金属部分的宽度大于不透明度金属部分; 以及对应于第一基板的第二基板。

15. 发明授权

US07838422B2 Al-doped charge trap layer, non-volatile memory device and methods of fabricating the same 有权
标题翻译： Al掺杂电荷陷阱层，非易失性存储器件及其制造方法
公开(公告)号：US07838422B2
公开(公告)日：2010-11-23
申请号：US11892849
申请日：2007-08-28
申请人： Eun-ha Lee , Hion-suck Baik , Kwang-soo Seol , Sang-jin Park , Jong-bong Park , Min-ho Yang
发明人： Eun-ha Lee , Hion-suck Baik , Kwang-soo Seol , Sang-jin Park , Jong-bong Park , Min-ho Yang
IPC分类号： H01L21/44
CPC分类号： H01L29/42332 , Y10T428/259
摘要： Provided is an aluminum (Al) doped charge trap layer, a non-volatile memory device and methods of fabricating the same. The charge trap layer may include a plurality of silicon nano dots that trap charges and a silicon oxide layer that covers the silicon nano dots, wherein the charge trap layer is doped with aluminum (Al). The non-volatile memory device may include a substrate including a source and a drain on separate regions of the substrate, a tunneling film on the substrate contacting the source and the drain, the charge trap layer according to example embodiments, a blocking film on the charge trap layer, and a gate electrode on the blocking film.
摘要翻译：提供了铝（Al）掺杂的电荷阱层，非易失性存储器件及其制造方法。电荷陷阱层可以包括捕获电荷的多个硅纳米点和覆盖硅纳米点的氧化硅层，其中电荷陷阱层掺杂有铝（Al）。非挥发性存储器件可以包括衬底，该衬底包括在衬底的分离区域上的源极和漏极，在衬底上接触源极和漏极的隧道膜，根据示例性实施例的电荷陷阱层，电荷陷阱层和阻挡膜上的栅电极。

16. 发明申请

US20100122716A1 WASHING DEVICE 有权
标题翻译：洗衣设备
公开(公告)号：US20100122716A1
公开(公告)日：2010-05-20
申请号：US12569272
申请日：2009-09-29
申请人： Tae Young Oh , Eun Ha Lee
发明人： Tae Young Oh , Eun Ha Lee
IPC分类号： B08B3/00
CPC分类号： H01L21/67034 , B08B3/10 , B08B7/0035 , G02F2001/1316 , H01L21/67028 , H01L21/67051 , H01L21/67115 , H01L21/6776 , H01L21/6838
摘要： A washing device is disclosed, which is capable of preventing damage of a substrate caused by drooping of the substrate. The washing device includes a plasma irradiating part supplied with a substrate from a substrate loading part to remove dirt from the substrate by irradiating plasma to the substrate; a dirt washing part supplied from the substrate from the plasma irradiating part to remove dirt remaining on the substrate; a finishing washing part supplied with the substrate from the dirt washing part to wash the substrate; a drying part supplied with the substrate from the finishing washing part to dry the substrate; and a substrate unloading part supplied with the substrate from the drying part to unload the substrate, wherein the plasma irradiating part includes a plasma irradiation unit that irradiates plasma to the substrate and a floating unit that maintains the substrate in a floating state.
摘要翻译：公开了一种清洗装置，其能够防止由于基板的下垂而造成的基板的损坏。洗涤装置包括从衬底装载部分提供有衬底的等离子体照射部分，以通过将等离子体照射到衬底来从衬底去除污物; 从所述基板从所述等离子体照射部供给的污物洗涤部，以去除残留在所述基板上的污物; 从污物清洗部分提供衬底以洗涤衬底的整理洗涤部分; 干燥部，其从所述精加工清洗部供给所述基板以干燥所述基板; 以及从干燥部供给基板以卸载基板的基板卸载部，其中等离子体照射部包括将等离子体照射到基板的等离子体照射单元和将基板保持在浮置状态的浮动单元。

17. 发明申请

US20100050364A1 Washing device 审中-公开
标题翻译：洗衣机
公开(公告)号：US20100050364A1
公开(公告)日：2010-03-04
申请号：US12314962
申请日：2008-12-19
申请人： Tae Young Oh , Hui Jae Lee , Geon Yong Kim , Eun Ha Lee
发明人： Tae Young Oh , Hui Jae Lee , Geon Yong Kim , Eun Ha Lee
IPC分类号： B08B5/02
CPC分类号： B08B5/02 , B08B5/023
摘要： A washing device capable of stably washing a substrate is disclosed. The washing device includes a substrate entry guiding unit which guides a substrate supplied from the outside to be entered in a correct direction, a dirt removing unit supplied with the substrate from the substrate entry guiding unit to remove dirt formed on the substrate, a dirt washing unit supplied with the substrate from the dirt removing unit to wash off residual dirt remaining on the substrate, and a position controlling unit controlling position of the substrate being discharged from the dirt washing unit.
摘要翻译：公开了能够稳定地洗涤基板的洗涤装置。洗涤装置包括：基板入口引导单元，其引导从正确方向从外部供应的基板;从基板输入引导单元提供有基板的污物去除单元，以去除基板上形成的污垢;污物洗涤从污物去除单元提供的基板的单元，以清除残留在基板上的残留污物;以及位置控制单元，控制从污物清洗单元排出的基板的位置。

18. 发明申请

US20070152283A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070152283A1
公开(公告)日：2007-07-05
申请号：US11551994
申请日：2006-10-23
申请人： Hion-suck BAIK , Eun-ha LEE , Hyung-suk JUNG , Sung-kee HAN , Min-ho YANG
发明人： Hion-suck BAIK , Eun-ha LEE , Hyung-suk JUNG , Sung-kee HAN , Min-ho YANG
IPC分类号： H01L29/94 , H01L21/3205
CPC分类号： H01L21/28556 , H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device and a manufacturing method thereof for preventing gate electrode degradation and gate current leakage. The semiconductor device includes a gate insulating layer including an H-k (high dielectric) material on a semiconductor substrate, a barrier metal layer including a metal alloy on the gate insulating layer, and a gate electrode layer formed on the barrier metal layer. Illustratively, the barrier metal layer includes at least one of TaAlN (tantalum aluminum nitride) or TiAlN (titanium aluminum nitride). The barrier metal layer can include an oxidation-resistant material so that oxidation of the barrier metal layer is prevented during a subsequent annealing of the semiconductor device in an oxygen atmosphere. Thus, degradation of a gate electrode is prevented, and gate current leakage due to degradation of the gate electrode is prevented.
摘要翻译：一种用于防止栅电极劣化和栅极电流泄漏的半导体器件及其制造方法。半导体器件包括在半导体衬底上包括H-k（高电介质）材料的栅极绝缘层，在栅极绝缘层上包括金属合金的阻挡金属层和形成在阻挡金属层上的栅电极层。说明性地，阻挡金属层包括TaAlN（氮化钽）或TiAlN（氮化铝）中的至少一种。阻挡金属层可以包括抗氧化材料，从而在半导体器件在氧气氛中的随后的退火中防止了阻挡金属层的氧化。因此，防止了栅电极的劣化，并且防止了由于栅电极的劣化引起的栅极电流泄漏。

19. 发明授权

US08618543B2 Thin film transistor including selectively crystallized channel layer and method of manufacturing the thin film transistor 有权
标题翻译：薄膜晶体管包括选择性结晶的沟道层和制造薄膜晶体管的方法
公开(公告)号：US08618543B2
公开(公告)日：2013-12-31
申请号：US11978581
申请日：2007-10-30
申请人： Eun-ha Lee , Dong-hun Kang , Jae-cheol Lee , Chang-jung Kim , Hyuck Lim
发明人： Eun-ha Lee , Dong-hun Kang , Jae-cheol Lee , Chang-jung Kim , Hyuck Lim
IPC分类号： H01L29/04
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02667 , H01L21/02672 , H01L21/02675
摘要： Provided are a thin film transistor (TFT) including a selectively crystallized channel layer, and a method of manufacturing the TFT. The TFT includes a gate, the channel layer, a source, and a drain. The channel layer is formed of an oxide semiconductor, and at least a portion of the channel layer contacting the source and the drain is crystallized. In the method of manufacturing the TFT, the channel layer is formed of an oxide semiconductor, and a metal component is injected into the channel layer so as to crystallize at least a portion of the channel layer contacting the source and the drain. The metal component can be injected into the channel layer by depositing and heat-treating a metal layer or by ion-implantation.
摘要翻译：提供了包括选择性晶化的沟道层的薄膜晶体管（TFT）和制造TFT的方法。 TFT包括栅极，沟道层，源极和漏极。沟道层由氧化物半导体形成，并且与源极和漏极接触的沟道层的至少一部分结晶。在制造TFT的方法中，沟道层由氧化物半导体形成，并且将金属成分注入到沟道层中，以便使与沟道层和漏极接触的沟道层的至少一部分结晶。可以通过沉积和热处理金属层或通过离子注入将金属成分注入到沟道层中。

20. 发明授权

US08440527B2 Memory device and method of fabricating the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US08440527B2
公开(公告)日：2013-05-14
申请号：US12659357
申请日：2010-03-05
申请人： Dong-Chul Yoo , Eun-Ha Lee , Hyung-Ik Lee , Ki-Hyun Hwang , Sung Heo , Han-Mei Choi , Yong-Koo Kyoung , Byong-Ju Kim
发明人： Dong-Chul Yoo , Eun-Ha Lee , Hyung-Ik Lee , Ki-Hyun Hwang , Sung Heo , Han-Mei Choi , Yong-Koo Kyoung , Byong-Ju Kim
IPC分类号： H01L29/788 , H01L29/792 , H01L29/66 , H01L21/336
CPC分类号： H01L27/11568 , H01L21/02145 , H01L21/022 , H01L21/0228 , H01L21/28282 , H01L21/3141 , H01L27/11521
摘要： A memory device and a method of fabricating the same are provided. The memory device includes a tunneling dielectric layer on a substrate, a charge storage layer on the tunneling dielectric layer, a blocking dielectric layer on the charge storage layer, the blocking dielectric layer including a first dielectric layer having silicon oxide, a second dielectric layer on the first dielectric layer and having aluminum silicate, and a third dielectric layer formed on the second dielectric layer and having aluminum oxide, and an upper electrode on the blocking dielectric layer.
摘要翻译：提供了一种存储器件及其制造方法。存储器件包括在衬底上的隧道电介质层，隧道电介质层上的电荷存储层，电荷存储层上的阻挡介电层，阻挡电介质层包括具有氧化硅的第一电介质层，所述第一电介质层具有硅酸铝，以及形成在所述第二电介质层上并具有氧化铝的第三电介质层和所述阻挡电介质层上的上电极。

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