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11. 发明授权

US06815941B2 Bandgap reference circuit 有权
标题翻译：带隙参考电路
公开(公告)号：US06815941B2
公开(公告)日：2004-11-09
申请号：US10358668
申请日：2003-02-05
申请人： Douglas Blaine Butler
发明人： Douglas Blaine Butler
IPC分类号： G05F316
CPC分类号： G05F3/30 , Y10S323/901
摘要： A bandgap reference circuit includes a current-voltage mirror circuit having first, second, third, and fourth nodes, a transistor having a current path coupled between a source of supply voltage and the first node, a current mirror portion having an input coupled to the first node and a control terminal coupled to the fourth node, a serially coupled first resistor and first diode coupled between the output of the current mirror portion and ground, a serially coupled second resistor and second diode coupled between the third node and ground, a third diode coupled between the second node and ground, and a differential amplifier having a first input coupled to the fourth node, a second input coupled to the output of the current mirror portion for generating a bandgap reference voltage, and an output coupled to the gate of the transistor.
摘要翻译：带隙参考电路包括具有第一，第二，第三和第四节点的电流 - 电压镜电路，晶体管具有耦合在电源电压源和第一节点之间的电流路径，电流镜部分具有耦合到第一节点和耦合到第四节点的控制端子，串联耦合的第一电阻器和耦合在电流镜部分的输出与地之间的第一二极管，耦合在第三节点和地之间的串联耦合的第二电阻器和第二二极管，耦合在第二节点和地之间的二极管和具有耦合到第四节点的第一输入的差分放大器，耦合到电流镜部分的输出端以产生带隙基准电压的第二输入端，以及耦合到第晶体管。

12. 发明授权

US07250795B2 High-speed, low-power input buffer for integrated circuit devices 有权
标题翻译：用于集成电路器件的高速，低功耗输入缓冲器
公开(公告)号：US07250795B2
公开(公告)日：2007-07-31
申请号：US11092506
申请日：2005-03-29
申请人： Douglas Blaine Butler
发明人： Douglas Blaine Butler
IPC分类号： H03B1/00
CPC分类号： G11C7/1078 , G11C7/1084
摘要： A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.
摘要翻译：用于集成电路器件的高速，低功耗输入缓冲器，其中输入电压（VIN）耦合到上拉和下拉晶体管。根据具体实施例，输入缓冲器在操作的校准阶段期间利用参考电压输入（VREF），但在主动操作模式中不使用输入缓冲器。当VIN = VREF时，在所有其他VIN电压下具有较低的通过电流电平时，提供最大电流通过电流。在包含所公开的输入缓冲器的集成电路装置中，每个器件输入引脚可以使用两个（或多个）输入缓冲器。

13. 发明授权

US07002874B1 Dual word line mode for DRAMs 有权
标题翻译： DRAM的双字线模式
公开(公告)号：US07002874B1
公开(公告)日：2006-02-21
申请号：US11081191
申请日：2005-03-16
申请人： Michael C. Parris , Douglas Blaine Butler , Oscar Frederick Jones, Jr.
发明人： Michael C. Parris , Douglas Blaine Butler , Oscar Frederick Jones, Jr.
IPC分类号： G11C8/10
CPC分类号： G11C8/10
摘要： An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to each data bit, and providing a word line sequence when first converting stored data in the array of memory cells from the first operational mode to the second operational mode. The word line sequence includes activating a first word line, developing a valid signal on a corresponding bit line, and then activating a second word line while the first word line is still active.
摘要翻译：集成电路存储器包括用于在每个位操作模式下单独激活第一个存储单元中的字线的电路，同时在第二操作模式中激活至少两个字线，其中两个或多个存储器单元专用于每个数据位，并提供一个当将存储单元阵列中的存储数据从第一操作模式转换为第二操作模式时，字线序列。字线序列包括激活第一字线，在对应位线上形成有效信号，然后在第一字线仍然有效时激活第二字线。

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