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11. 发明授权

US07711899B2 Information processing device and data control method in information processing device 有权
标题翻译：信息处理装置中的信息处理装置和数据控制方法
公开(公告)号：US07711899B2
公开(公告)日：2010-05-04
申请号：US11169858
申请日：2005-06-30
申请人： Takaharu Ishizuka , Daisuke Itou , Takashi Yamamoto
发明人： Takaharu Ishizuka , Daisuke Itou , Takashi Yamamoto
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0822
摘要： An information processing device of a multiprocessor configuration that can increase significantly the processing capability of read requests. The information processing device comprises a plurality of processing units, a plurality of cache memories for storing temporarily the data read by the plurality of processing units from respective main memories in combination with tag information indicating the state of the data that will be stored, and a system controller for controlling the access of the plurality of processing units to the main memories. The system controller comprises a tag copy unit for holding a copy of the tag information that will be stored in the cache memory, a plurality of write cues for storing write requests, and a store buffer for storing the arbitration results relating to a plurality of write requests that will be stored in the plurality of write cues.
摘要翻译：多处理器配置的信息处理设备可以显着增加读请求的处理能力。信息处理装置包括多个处理单元，多个高速缓冲存储器，用于暂时存储来自各个主存储器的多个处理单元读取的数据与表示将被存储的数据的状态的标签信息，以及系统控制器，用于控制多个处理单元对主存储器的访问。系统控制器包括用于保存将被存储在高速缓冲存储器中的标签信息的副本的标签复制单元，用于存储写请求的多个写入提示，以及用于存储与多个写入有关的仲裁结果的存储缓冲器将存储在多个写入提示中的请求。

12. 发明授权

US07694106B2 Multiprocessor system 有权
标题翻译：多处理器系统
公开(公告)号：US07694106B2
公开(公告)日：2010-04-06
申请号：US11785891
申请日：2007-04-20
申请人： Toshikazu Ueki , Takaharu Ishizuka , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Toshikazu Ueki , Takaharu Ishizuka , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F9/00
CPC分类号： G06F12/0813 , G06F12/1072
摘要： A multiprocessor system includes a judging unit judging whether a read command inputted to a global address crossbar is a read command to a memory on an own system board, an executing unit speculatively executing, when the judging unit judges that the read command is a read command to the memory on the own system board, the read command before global access based on an address notified from the global address crossbar, a setting unit setting for queuing data read from the memory in a data queue provided on a CPU without queuing the data in a data queue provided on the memory, and an instructing unit instructing, based on notification from the global address crossbar, the data queue provided on the CPU to discard the data or transmit the data to the CPU.
摘要翻译：多处理器系统包括判断单元，判断单元判断输入到全局地址交叉开关的读取命令是否是对自身系统板上的存储器的读取命令，当判断单元判断读取命令是读取命令时，执行单元推测执行基于从全局地址交叉开关通知的地址，在全局访问之前的读取命令，在CPU上提供的数据队列中从存储器读取数据的设置单元设置，而不排队数据设置在存储器上的数据队列，以及指示单元，根据来自全局地址交叉开关的通知指示CPU上提供的数据队列，丢弃数据或将数据发送到CPU。

13. 发明申请

US20100077262A1 INFORMATION PROCESSING DEVICE AND ERROR PROCESSING METHOD 失效
标题翻译：信息处理设备和错误处理方法
公开(公告)号：US20100077262A1
公开(公告)日：2010-03-25
申请号：US12554318
申请日：2009-09-04
申请人： Atsushi MOROSAWA , Takaharu ISHIZUKA , Toshikazu UEKI , Makoto HATAIDA , Yuka HOSOKAWA , Takeshi OWAKI , Takashi YAMAMOTO , Daisuke ITOU
发明人： Atsushi MOROSAWA , Takaharu ISHIZUKA , Toshikazu UEKI , Makoto HATAIDA , Yuka HOSOKAWA , Takeshi OWAKI , Takashi YAMAMOTO , Daisuke ITOU
IPC分类号： G06F11/00
CPC分类号： G06F11/1658 , G06F11/1641 , G06F11/165 , G06F11/1687
摘要： An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.
摘要翻译：具有能够彼此同步操作的两个处理单元的信息处理装置包括：能够向两个处理单元输出相同信号的公共单元; 分别提供给处理单元的检测单元，并分别检测相应处理单元中发生的错误; 比较来自两个处理单元的输出的比较单元; 以及控制单元，其基于检测单元的检测结果和比较单元的比较结果来控制从处理单元到公共单元的信号，并且如果检测单元同时检测到相同类型的错误，则确定，错误是由于公共单元的错误。

14. 发明申请

US20080046694A1 Multiprocessor system 有权
标题翻译：多处理器系统
公开(公告)号：US20080046694A1
公开(公告)日：2008-02-21
申请号：US11785891
申请日：2007-04-20
申请人： Toshikazu Ueki , Takaharu Ishizuka , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Toshikazu Ueki , Takaharu Ishizuka , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F9/30
CPC分类号： G06F12/0813 , G06F12/1072
摘要： A multiprocessor system includes a judging unit judging whether a read command inputted to a global address crossbar is a read command to a memory on an own system board, an executing unit speculatively executing, when the judging unit judges that the read command is a read command to the memory on the own system board, the read command before global access based on an address notified from the global address crossbar, a setting unit setting for queuing data read from the memory in a data queue provided on a CPU without queuing the data in a data queue provided on the memory, and an instructing unit instructing, based on notification from the global address crossbar, the data queue provided on the CPU to discard the data or transmit the data to the CPU.
摘要翻译：多处理器系统包括判断单元，判断单元判断输入到全局地址交叉开关的读取命令是否是对自身系统板上的存储器的读取命令，当判断单元判断读取命令是读取命令时，执行单元推测执行基于从全局地址交叉开关通知的地址，在全局访问之前的读取命令，在CPU上提供的数据队列中从存储器读取数据的设置单元设置，而不排队数据设置在存储器上的数据队列，以及指示单元，根据来自全局地址交叉开关的通知指示CPU上提供的数据队列，丢弃数据或将数据发送到CPU。

15. 发明授权

US07237955B2 Hydrodynamic bearing and disc rotation apparatus using the same 有权
标题翻译：流体动力轴承和使用其的盘旋转装置
公开(公告)号：US07237955B2
公开(公告)日：2007-07-03
申请号：US10727070
申请日：2003-12-02
申请人： Takafumi Asada , Hiroaki Saito , Keigo Kusaka , Daisuke Itou
发明人： Takafumi Asada , Hiroaki Saito , Keigo Kusaka , Daisuke Itou
IPC分类号： F16C32/06
CPC分类号： F16C33/107 , F16C17/045 , F16C17/107 , F16C2370/12 , G11B19/2018
摘要： A high-accuracy, long-life hydrodynamic bearing that does not cause oil film breakage in bearing clearances and a disc rotation apparatus using the bearing is disclosed. Oil film breakage is avoided as negative pressure is prevented from generating between the shaft and sleeve of the hydrodynamic bearing. Herringbone shaped dynamic pressure generating grooves, located on the thrust bearing section and the radial bearing section of the hydrodynamic bearing, are oil filled and have optimum shapes. The optimum shapes prevent the generation negative pressure and thus prevents the coagulation of air bubbles that can cause oil film breakage. The disc rotation apparatus, that holds a reproduction/recording disc, is concentrically secured to the hydrodynamic bearing and rotated. The disc is put into contact with magnetic or optical heads while rotating in the disc rotation apparatus. Both the hydrodynamic bearing and the disc rotation apparatus experience high reliability.
摘要翻译：公开了一种高精度，长寿命的流体动力轴承，其不会导致轴承间隙中的油膜破裂和使用轴承的盘旋转装置。避免了油膜断裂，因为防止在流体动力轴承的轴和套筒之间产生负压。位于推力轴承部分和流体动力轴承的径向轴承部分的人字形动态压力产生槽被充满油并具有最佳形状。最佳形状可以防止发生负压，从而防止会导致油膜破裂的气泡凝结。保持再现/记录盘的盘旋转装置同心地固定到流体动力轴承并旋转。在盘旋转装置中旋转时，盘与磁头或光头接触。流体动力轴承和圆盘旋转装置都具有高可靠性。

16. 发明申请

US20060212652A1 Information processing device and data control method in information processing device 有权
标题翻译：信息处理装置中的信息处理装置和数据控制方法
公开(公告)号：US20060212652A1
公开(公告)日：2006-09-21
申请号：US11169858
申请日：2005-06-30
申请人： Takaharu Ishizuka , Daisuke Itou , Takashi Yamamoto
发明人： Takaharu Ishizuka , Daisuke Itou , Takashi Yamamoto
IPC分类号： G06F12/00 , G06F13/28
CPC分类号： G06F12/0822
摘要： An information processing device of a multiprocessor configuration that can increase significantly the processing capability of read requests. The information processing device comprises a plurality of processing units, a plurality of cache memories for storing temporarily the data read by the plurality of processing units from respective main memories in combination with tag information indicating the state of the data that will be stored, and a system controller for controlling the access of the plurality of processing units to the main memories. The system controller comprises a tag copy unit for holding a copy of the tag information that will be stored in the cache memory, a plurality of write cues for storing write requests, and a store buffer for storing the arbitration results relating to a plurality of write requests that will be stored in the plurality of write cues.
摘要翻译：多处理器配置的信息处理设备可以显着增加读请求的处理能力。信息处理装置包括多个处理单元，多个高速缓存存储器，用于暂时存储来自各个主存储器的多个处理单元读取的数据与表示将被存储的数据的状态的标签信息，以及系统控制器，用于控制多个处理单元对主存储器的访问。系统控制器包括用于保存将被存储在高速缓冲存储器中的标签信息的副本的标签复制单元，用于存储写入请求的多个写入提示，以及用于存储与多个写入有关的仲裁结果的存储缓冲器将存储在多个写入提示中的请求。

17. 发明授权

US08775891B2 Transmission device, receiving circuit and control method of transmission device 失效
标题翻译：传输设备，接收电路和传输设备的控制方法
公开(公告)号：US08775891B2
公开(公告)日：2014-07-08
申请号：US12763551
申请日：2010-04-20
申请人： Junji Ichimiya , Hiroshi Nakayama , Daisuke Itou , Shintaro Itozawa
发明人： Junji Ichimiya , Hiroshi Nakayama , Daisuke Itou , Shintaro Itozawa
IPC分类号： H04L1/18
CPC分类号： H04L1/1854
摘要： A transmitting circuit transmits data to which an error detection code is attached to a receiving circuit via a transmission path. When detecting the error of the data received via the transmission path, a receiving circuit transmits a retransmit request for the data in which the error is detected to the transmitting circuit. The receiving circuit enters a termination unit adjustment period using the error detection of the received data as a trigger and updates the resistance values of a receiving side termination unit installed at the termination of the transmission path to an appropriate value within the termination unit adjustment period.
摘要翻译：发送电路经由传输路径发送附加了错误检测码的数据到接收电路。当检测到通过传输路径接收到的数据的错误时，接收电路向发送电路发送检测到错误的数据的重传请求。接收电路使用接收到的数据的错误检测作为触发进入终端单元调整周期，并且将在传输路径的终止处安装的接收侧终端单元的电阻值更新为终止单元调整周期内的适当值。

18. 发明授权

US08181064B2 Information processing apparatus for inhibiting instructions, saving and restoring internal information in response to abnormality in redundant processor system 失效
标题翻译：用于抑制指令的信息处理装置，响应于冗余处理器系统的异常而保存和恢复内部信息
公开(公告)号：US08181064B2
公开(公告)日：2012-05-15
申请号：US12659896
申请日：2010-03-24
申请人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
发明人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
IPC分类号： G06F11/00
CPC分类号： G06F11/1658 , G06F11/165 , G06F11/1679 , G06F2201/81
摘要： A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in a firmware hub instructs the northbridge to inhibit an external instruction. In addition, the firmware saves the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU saved on the memory to all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.
摘要翻译：当检测到冗余CPU的同步中断时，北桥停止发生错误的异常CPU总线的操作，并且固件集线器中的固件指示北桥禁止外部指令。此外，固件还可以将连接到普通CPU总线的普通CPU的内部信息和高速缓存数据保存在存储器上，并且北桥将重置到家庭系统板中的所有CPU。然后，固件将保存在存储器上的CPU的内部信息恢复到所有CPU，并指示北桥取消对外部指令的禁止。

19. 发明授权

US08159140B2 Load driving apparatus 有权
标题翻译：负载驱动装置
公开(公告)号：US08159140B2
公开(公告)日：2012-04-17
申请号：US12553361
申请日：2009-09-03
申请人： Go Takata , Shinichiro Kataoka , Yasunori Yamamoto , Tsukasa Kawahara , Ryuji Ueda , Daisuke Itou
发明人： Go Takata , Shinichiro Kataoka , Yasunori Yamamoto , Tsukasa Kawahara , Ryuji Ueda , Daisuke Itou
IPC分类号： H05B37/00
CPC分类号： H05B33/0815 , H05B33/0824
摘要： The load driving apparatus according to the present invention includes a load current setting signal generating section, a load current generating section, a reference voltage generating section and a drive voltage generating section. The load current setting signal generating section generates a desired load current setting signal. The load current generating section generates a load current based on the load current setting signal to drive the load. The reference voltage generating section generates a reference voltage based on the load current setting signal. The drive voltage generating section generates a drive voltage, supplies the drive voltage to the load, generates a between-both-terminals voltage between both terminals of the load current generating section based on the drive voltage and controls the drive voltage so that the difference between the between-both-terminals voltage and the reference voltage becomes small.
摘要翻译：根据本发明的负载驱动装置包括负载电流设定信号生成部，负载电流产生部，基准电压生成部和驱动电压生成部。负载电流设定信号生成部生成期望的负载电流设定信号。负载电流产生部根据负载电流设定信号生成负载电流，驱动负载。参考电压产生部分基于负载电流设置信号产生参考电压。驱动电压产生部生成驱动电压，向驱动电压供给驱动电压，根据驱动电压在负载电流产生部的两端之间产生两端电压，并控制驱动电压，两端电压和参考电压变小。

20. 发明授权

US08090912B2 Multiprocessor system, system board, and cache replacement request handling method 有权
标题翻译：多处理器系统，系统板和缓存替换请求处理方法
公开(公告)号：US08090912B2
公开(公告)日：2012-01-03
申请号：US11790265
申请日：2007-04-24
申请人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0833
摘要： A request issued by the CPU is output from the local arbiter by way of the CPU bus and the CPU-issued request queue. The cache replacement request loop-back circuit determines at the loop-back determination circuit whether the outputted request is a cache replacement request or not. A request other than a cache replacement request is output onto the local bus. A cache replacement request is output to the selector and sent to the request handling section when there is no valid request on the global bus.
摘要翻译：通过CPU总线和CPU发出的请求队列，从本地仲裁器输出CPU发出的请求。高速缓存替换请求环回电路在环回确定电路中确定输出的请求是否是高速缓存替换请求。除了缓存替换请求之外的请求被输出到本地总线上。当全局总线上没有有效请求时，高速缓存替换请求被输出到选择器并发送到请求处理部分。

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