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11. 发明申请

US20100208526A1 Non-volatile memory device and method of operation therefor 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20100208526A1
公开(公告)日：2010-08-19
申请号：US12662571
申请日：2010-04-23
申请人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
发明人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
IPC分类号： G11C16/14
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line; and the de-coupling transistor is formed in the well.
摘要翻译：在一个实施例中，非易失性存储器件包括形成在衬底中的第一导电类型的阱以及与阱中形成的位线串联连接的第一多个存储单元晶体管。在阱外部的衬底中形成缓冲器，并连接到位线。至少一个去耦合晶体管被配置为从位线去耦合缓冲器; 并且在阱中形成去耦合晶体管。

12. 发明授权

US07749840B2 Methods of forming a semiconductor device including buried bit line 有权
标题翻译：形成包括掩埋位线的半导体器件的方法
公开(公告)号：US07749840B2
公开(公告)日：2010-07-06
申请号：US11757906
申请日：2007-06-04
申请人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
发明人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
IPC分类号： H01L21/336 , H01L21/425 , H01L21/44
CPC分类号： H01L27/10885 , H01L27/10876
摘要： A method of forming a buried interconnection includes removing a semiconductor substrate to form a groove in the semiconductor substrate. A metal layer is formed on inner walls of the groove using an electroless deposition technique. A silicidation process is applied to the substrate having the metal layer, thereby forming a metal silicide layer on the inner walls of the groove.
摘要翻译：形成掩埋布线的方法包括去除半导体衬底以在半导体衬底中形成凹槽。使用无电沉积技术在凹槽的内壁上形成金属层。对具有金属层的基板进行硅化处理，从而在槽的内壁上形成金属硅化物层。

13. 发明申请

US20090191699A1 METHODS FOR FORMING SILICIDE CONDUCTORS USING SUBSTRATE MASKING 有权
标题翻译：使用基板掩模形成硅胶导体的方法
公开(公告)号：US20090191699A1
公开(公告)日：2009-07-30
申请号：US12276562
申请日：2008-11-24
申请人： Eun-ji Jung , Dae-yong Kim , Gil-heyun Choi , Byung-hee Kim , Woong-hee Sohn , Hyun-su Kim , Jang-hee Lee , Eun-ok Lee , Jeong-gil Lee
发明人： Eun-ji Jung , Dae-yong Kim , Gil-heyun Choi , Byung-hee Kim , Woong-hee Sohn , Hyun-su Kim , Jang-hee Lee , Eun-ok Lee , Jeong-gil Lee
IPC分类号： H01L21/28
CPC分类号： H01L21/28052 , H01L29/66545
摘要： A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.
摘要翻译：多个间隔开的导体结构形成在半导体衬底上，每个导体结构包括导电层。绝缘垫片形成在导体结构的侧壁上。形成填充相邻绝缘间隔件之间的间隙的层间绝缘膜。去除层间绝缘层的一部分以暴露导电层的上表面。相应的外延层在导电层的相应暴露的上表面上生长，并且各自的外延层形成各自的金属硅化物层。

14. 发明授权

US07470612B2 Method of forming metal wiring layer of semiconductor device 有权
标题翻译：形成半导体器件金属布线层的方法
公开(公告)号：US07470612B2
公开(公告)日：2008-12-30
申请号：US11519844
申请日：2006-09-13
申请人： Kyung-in Choi , Sung-ho Han , Sang-woo Lee , Dae-yong Kim
发明人： Kyung-in Choi , Sung-ho Han , Sang-woo Lee , Dae-yong Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76868 , H01L21/76876 , H01L21/76879 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal wiring layer of a semiconductor device produces metal wiring that is free of defects. The method includes forming an insulating layer pattern defining a recess on a substrate, forming a conformal first barrier metal layer on the insulating layer pattern, and forming a second barrier metal layer on the first barrier metal layer in such a way that the second barrier metal layer will facilitate the growing of metal from the bottom of the recess such that the metal can fill a bottom part of the recess completely and thus, form damascene wiring. An etch stop layer pattern is formed after the damascene wiring is formed so as to fill the portion of the recess which is not occupied by the damascene wiring.
摘要翻译：形成半导体器件的金属布线层的方法产生没有缺陷的金属布线。该方法包括形成在衬底上限定凹陷的绝缘层图案，在绝缘层图案上形成共形的第一阻挡金属层，并在第一阻挡金属层上形成第二阻挡金属层，使得第二阻挡金属层将有助于从凹部的底部生长金属，使得金属可以完全填充凹部的底部，从而形成镶嵌线。在形成镶嵌线之后形成蚀刻停止层图案，以便填充未被镶嵌布线占据的凹部的部分。

15. 发明申请

US20070295995A1 METHODS OF FORMING A SEMICONDUCTOR DEVICE INCLUDING BURIED BIT LINES 有权
标题翻译：形成包含BINIIT位线的半导体器件的方法
公开(公告)号：US20070295995A1
公开(公告)日：2007-12-27
申请号：US11757906
申请日：2007-06-04
申请人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
发明人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
IPC分类号： H01L27/10 , H01L21/44
CPC分类号： H01L27/10885 , H01L27/10876
摘要： A method of forming a buried interconnection includes removing a semiconductor substrate to form a groove in the semiconductor substrate. A metal layer is formed on inner walls of the groove using an electroless deposition technique. A silicidation process is applied to the substrate having the metal layer, thereby forming a metal silicide layer on the inner walls of the groove.
摘要翻译：形成掩埋布线的方法包括去除半导体衬底以在半导体衬底中形成凹槽。使用无电沉积技术在凹槽的内壁上形成金属层。对具有金属层的基板进行硅化处理，从而在槽的内壁上形成金属硅化物层。

16. 发明申请

US20070285861A1 Over-voltage protection circuit and method thereof 有权
标题翻译：过电压保护电路及其方法
公开(公告)号：US20070285861A1
公开(公告)日：2007-12-13
申请号：US11790361
申请日：2007-04-25
申请人： Dae-yong Kim
发明人： Dae-yong Kim
IPC分类号： H02H3/20 , H02H3/06 , H03K19/003
CPC分类号： H03K19/00361
摘要： Example embodiments are directed to an over-voltage protection circuit and method thereof. The over-voltage protection circuit may include a voltage converter, a voltage comparator, a delay unit, and/or a switching unit. The voltage converter may be configured to generate first voltage and second voltages from a supply voltage. The voltage comparator may be configured to compare the first voltage with the second voltage and to generate a control signal according to the comparison result. The switching unit may be configured to determine whether to apply the supply voltage to a chip in response to the control signal. The delay unit may be configured to delay transmission of the control signal to the switching unit by a delay time.
摘要翻译：示例性实施例涉及过电压保护电路及其方法。过电压保护电路可以包括电压转换器，电压比较器，延迟单元和/或开关单元。电压转换器可以被配置为从电源电压产生第一电压和第二电压。电压比较器可以被配置为将第一电压与第二电压进行比较，并且根据比较结果产生控制信号。开关单元可以被配置为响应于控制信号来确定是否将电源电压施加到芯片。延迟单元可以被配置为延迟控制信号到开关单元的延迟时间的传输。

17. 发明授权

US07230251B2 Electron beam lens for micro-column electron beam apparatus and method of fabricating the same 有权
标题翻译：用于微柱电子束装置的电子束透镜及其制造方法
公开(公告)号：US07230251B2
公开(公告)日：2007-06-12
申请号：US11174891
申请日：2005-07-01
申请人： Sang Kuk Choi , Dae Yong Kim
发明人： Sang Kuk Choi , Dae Yong Kim
IPC分类号： H01J37/12
CPC分类号： H01J9/02 , H01J3/18 , H01J9/14 , H01J37/12 , H01J2237/1205 , H01J2237/3175 , H01J2237/31754 , Y10T29/49117
摘要： Provided is an electron beam lens for a micro-column electron beam apparatus and a method of manufacturing the same. A photosensitive glass substrate is used as a base isolation substrate and a thin metal film is grown by a plating method. Holes through which electron beam passes are formed by a lift off method after forming a resist pattern shaped as a hole on a seed metal layer and plating the thin metal film.
摘要翻译：本发明提供一种微柱电子束装置用电子束透镜及其制造方法。使用感光性玻璃基板作为基底隔离基板，通过电镀法生长金属薄膜。在种子金属层上形成形成为孔的抗蚀剂图案并镀覆薄金属膜之后，通过剥离法形成电子束通过的孔。

18. 发明申请

US20070059925A1 Method of forming metal wiring layer of semiconductor device 有权
标题翻译：形成半导体器件金属布线层的方法
公开(公告)号：US20070059925A1
公开(公告)日：2007-03-15
申请号：US11519844
申请日：2006-09-13
申请人： Kyung-in Choi , Sung-ho Han , Sang-woo Lee , Dae-yong Kim
发明人： Kyung-in Choi , Sung-ho Han , Sang-woo Lee , Dae-yong Kim
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76868 , H01L21/76876 , H01L21/76879 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal wiring layer of a semiconductor device produces metal wiring that is free of defects. The method includes forming an insulating layer pattern defining a recess on a substrate, forming a conformal first barrier metal layer on the insulating layer pattern, and forming a second barrier metal layer on the first barrier metal layer in such a way that the second barrier metal layer will facilitate the growing of metal from the bottom of the recess such that the metal can fill a bottom part of the recess completely and thus, form damascene wiring. An etch stop layer pattern is formed after the damascene wiring is formed so as to fill the portion of the recess which is not occupied by the damascene wiring.
摘要翻译：形成半导体器件的金属布线层的方法产生没有缺陷的金属布线。该方法包括形成在衬底上限定凹陷的绝缘层图案，在绝缘层图案上形成共形的第一阻挡金属层，并在第一阻挡金属层上形成第二阻挡金属层，使得第二阻挡金属层将有助于从凹部的底部生长金属，使得金属可以完全填充凹部的底部，从而形成镶嵌线。在形成镶嵌线之后形成蚀刻停止层图案，以便填充未被镶嵌布线占据的凹部的部分。

19. 发明申请

US20060223249A1 Semiconductor device multilayer structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method 有权
标题翻译：半导体器件多层结构，其制造方法，具有该半导体器件的半导体器件的半导体器件制造方法
公开(公告)号：US20060223249A1
公开(公告)日：2006-10-05
申请号：US11214680
申请日：2005-08-29
申请人： Jae-Hwa Park , Hee-Sook Park , Dae-Yong Kim , Jang-Hee Lee
发明人： Jae-Hwa Park , Hee-Sook Park , Dae-Yong Kim , Jang-Hee Lee
IPC分类号： H01L21/8234
CPC分类号： H01L21/823828 , H01L21/823835 , H01L21/823842
摘要： In one embodiment, a semiconductor device comprises a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped conductive layer. The diffusion barrier layer comprises an amorphous semiconductor material. An ohmic contact layer is formed over the diffusion barrier layer. A metal barrier layer is formed over the ohmic contact layer. A metal layer is formed over the metal barrier layer.
摘要翻译：在一个实施例中，半导体器件包括形成在半导体衬底上的半导体衬底和掺杂导电层。在掺杂导电层上方形成扩散阻挡层。扩散阻挡层包括非晶半导体材料。在扩散阻挡层上形成欧姆接触层。金属阻挡层形成在欧姆接触层上。在金属阻挡层上形成金属层。

20. 发明授权

US06404011B2 Semiconductor power integrated circuit 有权
标题翻译：半导体电源集成电路
公开(公告)号：US06404011B2
公开(公告)日：2002-06-11
申请号：US09865004
申请日：2001-05-23
申请人： Jong-Dae Kim , Sang-Gi Kim , Jin-Gun Koo , Dae-Yong Kim
发明人： Jong-Dae Kim , Sang-Gi Kim , Jin-Gun Koo , Dae-Yong Kim
IPC分类号： H01L2976
CPC分类号： H01L21/84 , H01L21/76264 , H01L21/76283 , H01L27/1203
摘要： A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.
摘要翻译：一种制造半导体功率集成电路的方法包括以下步骤：形成具有至少一个有源区的半导体结构，其中有源区包括用于形成源的阱区和用于形成漏极区的漂移区，形成用于有源区的隔离，其中沟槽具有来自半导体结构的表面的预定深度，在沟槽内部和半导体结构之上形成第一TEOS氧化物层，其中第一TEOS氧化物层具有来自该半导体结构的预定厚度在所述第一TEOS氧化物层上形成第二TEOS氧化物层，其中所述第二TEOS氧化物层的厚度小于所述第一TEOS氧化物层的厚度，并且对所述第一TEOS氧化物层进行选择性蚀刻第一和第二TEOS氧化物层，从而同时形成场氧化物层图案，二极管绝缘层图案和栅极氧化物层图案 y减少加工步骤并获得低导通电阻。

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