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    • 8. 发明授权
    • Semiconductor device and method of fabricating the same
    • 半导体装置及其制造方法
    • US07638433B2
    • 2009-12-29
    • US11965420
    • 2007-12-27
    • Jong-Ho YunGil-Heyun ChoiByung-Hee KimHyun-Su KimEun-Ok Lee
    • Jong-Ho YunGil-Heyun ChoiByung-Hee KimHyun-Su KimEun-Ok Lee
    • H01L21/302H01L21/461H01L29/40
    • H01L21/28097H01L29/4975H01L29/66545
    • A method of fabricating a semiconductor device includes forming a preliminary gate pattern on a semiconductor substrate. The preliminary gate pattern includes a gate oxide pattern, a conductive pattern, and a sacrificial insulating pattern. The method further includes forming spacers on opposite sidewalls of the preliminary gate pattern, forming an interlayer dielectric pattern to expose the sacrificial insulating pattern, removing the sacrificial insulating pattern to form an opening to expose the conductive pattern, transforming the conductive pattern into a metal silicide layer and forming a metal barrier pattern along an inner profile of the opening and a metal conductive pattern to fill the opening including the metal barrier pattern. The metal silicide layer and the metal conductive pattern constitute a gate electrode.
    • 制造半导体器件的方法包括在半导体衬底上形成初步栅极图案。 初步栅极图案包括栅极氧化物图案,导电图案和牺牲绝缘图案。 该方法还包括在初步栅极图案的相对侧壁上形成间隔物,形成层间电介质图案以暴露牺牲绝缘图案,去除牺牲绝缘图案以形成露出导电图案的开口,将导电图案转变为金属硅化物 并且沿着开口的内部轮廓形成金属阻挡图案和金属导电图案以填充包括金属阻挡图案的开口。 金属硅化物层和金属导电图案构成栅电极。
    • 10. 发明申请
    • METHODS OF FORMING WIRING STRUCTURES
    • 形成接线结构的方法
    • US20110092060A1
    • 2011-04-21
    • US12836081
    • 2010-07-14
    • Eun-Ok LeeDae-Yong KimGil-Heyun ChoiByung-Hee Kim
    • Eun-Ok LeeDae-Yong KimGil-Heyun ChoiByung-Hee Kim
    • H01L21/768H01L21/28
    • H01L29/66621H01L21/76831H01L21/76885H01L21/76889H01L21/76897H01L27/10814H01L27/10855H01L27/10885H01L27/10888H01L27/10894H01L29/4236H01L29/665H01L29/78
    • A semiconductor memory wiring method includes: receiving a substrate having a cell array region and a peripheral circuit region; depositing a first insulating layer on the substrate; forming a first contact plug in the cell array region, the first contact plug having a first conductive material extending through the first insulating layer; forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line having the first conductive material directly covering and integrated with the first contact plug; forming a second contact plug in the peripheral circuit region at substantially the same time as forming the first contact plug, the second contact plug having the first conductive material extending through the first insulating layer; and forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line having the first conductive material directly covering and integrated with the second contact plug.
    • 一种半导体存储器布线方法,包括:接收具有单元阵列区域和外围电路区域的基板; 在衬底上沉积第一绝缘层; 在所述电池阵列区域中形成第一接触插塞,所述第一接触插塞具有延伸穿过所述第一绝缘层的第一导电材料; 在形成第一接触插塞的基本上同时形成第一细长导线,所述第一细长导线具有直接覆盖并与第一接触插塞一体化的第一导电材料; 在形成第一接触插塞的基本上相同的时间在外围电路区域中形成第二接触插塞,第二接触插塞具有延伸穿过第一绝缘层的第一导电材料; 并且在与形成所述第二接触插塞的基本同时形成第二细长导电线,所述第二细长导电线具有直接覆盖并与所述第二接触插塞一体化的所述第一导电材料。