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11. 发明授权

US08399269B2 LED flip-chip package structure with dummy bumps 有权
标题翻译： LED倒装芯片封装结构，带虚拟凸块
公开(公告)号：US08399269B2
公开(公告)日：2013-03-19
申请号：US13474282
申请日：2012-05-17
申请人： Chung-Yu Wang
发明人： Chung-Yu Wang
IPC分类号： H01L21/00
CPC分类号： H01L33/62 , H01L24/17 , H01L33/486 , H01L33/54 , H01L33/642 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/49107 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/00014 , H01L2924/00
摘要： A light-emitting device (LED) package component includes an LED chip having a first active bond pad and a second active bond pad. A carrier chip is bonded onto the LED chip through flip-chip bonding. The carrier chip includes a first active through-substrate via (TSV) and a second active TSV connected to the first and the second active bond pads, respectively. The carrier chip further includes a dummy TSV therein, which is electrically coupled to the first active bond pad, and is configured not to conduct any current when a current flows through the LED chip.
摘要翻译：发光器件（LED）封装部件包括具有第一有源接合焊盘和第二有源接合焊盘的LED芯片。载体芯片通过倒装芯片接合结合到LED芯片上。载体芯片包括分别连接到第一和第二有源接合焊盘的第一有源通过衬底通孔（TSV）和第二有源TSV。载体芯片还包括其中的虚拟TSV，其电耦合到第一有源接合焊盘，并且被配置为在电流流过LED芯片时不导通任何电流。

12. 发明申请

US20120204951A1 PHOSPHOR-CONTAINED SOLAR CELL AND METHOD THEREOF 审中-公开
标题翻译：含磷光体的太阳能电池及其方法
公开(公告)号：US20120204951A1
公开(公告)日：2012-08-16
申请号：US13302378
申请日：2011-11-22
申请人： Chung-Yu WANG , Yi-Fang CHEN
发明人： Chung-Yu WANG , Yi-Fang CHEN
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： H01L31/055 , Y02E10/52
摘要： A phosphor-contained solar cell comprises a photoelectric conversion layer for conversing the photo energy to electrical energy; a phosphor layer, disposed on at least one side of the photoelectric conversion layer, for improving the photoelectric conversion efficiency; the phosphor is up conversion phosphor or down conversion phosphor; wherein the up conversion phosphor is selected from X2Mo2O9:X or X2Mo2O9:X,X; the down-conversion phosphor is selected from JQX(PO4)2:X3+ or JQX(PO4)2:X2+,X2+; wherein X represents anyone of rare earth metal, J represents lithium, sodium or potassium, Q represents anyone of alkaline earth metal.
摘要翻译：含磷光体的太阳能电池包括用于将光能转换成电能的光电转换层; 荧光体层，设置在所述光电转换层的至少一侧，用于提高光电转换效率; 磷光体是上变换磷光体或下变换磷光体; 其中上转换荧光体选自X2Mo2O9：X或X2Mo2O9：X，X; 下转换荧光体选自JQX（PO4）2：X3 +或JQX（PO4）2：X2 +，X2 +; 其中X表示任何稀土金属，J表示锂，钠或钾，Q表示任何碱土金属。

13. 发明申请

US20120097986A1 WAFER LEVEL REFLECTOR FOR LED PACKAGING 有权
标题翻译： LED包装用水平反射器
公开(公告)号：US20120097986A1
公开(公告)日：2012-04-26
申请号：US12910363
申请日：2010-10-22
申请人： Hao-Wei KU , Chung Yu WANG , Yu-Sheng Tang , Hsin-Hung Chen , Hao-Yu Yang , Ching-Yi Chen , Hsiao-Wen Lee , Chi Xiang Tseng , Sheng-Shin Guo , Tien-Ming Lin , Shang-Yu Tsai
发明人： Hao-Wei KU , Chung Yu WANG , Yu-Sheng Tang , Hsin-Hung Chen , Hao-Yu Yang , Ching-Yi Chen , Hsiao-Wen Lee , Chi Xiang Tseng , Sheng-Shin Guo , Tien-Ming Lin , Shang-Yu Tsai
IPC分类号： H01L33/60 , H01L21/56
CPC分类号： H01L27/15 , H01L24/97 , H01L25/167 , H01L33/486 , H01L33/54 , H01L33/60 , H01L2224/48091 , H01L2224/48227 , H01L2224/8592 , H01L2924/01322 , H01L2924/10253 , H01L2924/12035 , H01L2924/12041 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2933/0033 , H01L2933/005 , H01L2933/0058 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： An optical emitter is fabricated by bonding a Light-Emitting Diode (LED) die to a package wafer, electrically connecting the LED die and the package wafer, forming a phosphor coating over the LED die on the package wafer, molding a lens over the LED die on the package wafer, molding a reflector on the package wafer, and dicing the wafer into at least one optical emitter.
摘要翻译：通过将发光二极管（LED）裸片结合到封装晶片，电连接LED管芯和封装晶片，在封装晶片上的LED管芯上形成荧光体涂层，在LED上模制透镜来制造光发射器在封装晶片上模制，在封装晶片上模制反射器，并将晶片切割成至少一个光发射器。

14. 发明申请

US20110292646A1 Structure of lighting device 有权
标题翻译：照明装置结构
公开(公告)号：US20110292646A1
公开(公告)日：2011-12-01
申请号：US12801703
申请日：2010-06-22
申请人： Chih-Hsien Wu , Meng-Chieh Chou , Chung-Yu Wang
发明人： Chih-Hsien Wu , Meng-Chieh Chou , Chung-Yu Wang
IPC分类号： F21V29/00 , F21S4/00
CPC分类号： F21V19/0055 , F21K9/27 , F21V19/0045 , F21V29/507 , F21V29/70 , F21V29/83 , F21Y2103/10 , F21Y2115/10
摘要： A structure of lighting device includes g a hood, a heat dissipater, at least one substrate board, and a fastener. The hood forms a receiving space, at least one fitting slot, and at least one heat dissipation opening. The fitting slot is located inside the receiving space. The heat dissipation opening is defined in a circumferential surface of the hood. The heat dissipater is received in the receiving space. The heat dissipater forms at least one guide section. The guide section opposes the fitting slot and is received in the fitting slot. The substrate board is electrically connected to at least one light-emitting diode. The substrate board is coupled to the heat dissipater. The heat dissipation opening allows for air circulation for removing heat generated by light-emitting diodes. Further, the heat dissipation opening is formed to have a width W less than 3mm, and the heat dissipater is arranged to be spaced from a circumferential surface of the hood by a distance greater than 6mm.
摘要翻译：照明装置的结构包括罩，散热器，至少一个基板和紧固件。罩形成容纳空间，至少一个装配槽和至少一个散热开口。配件槽位于接收空间内。散热口限定在罩的圆周表面。散热器被接收在接收空间中。散热器形成至少一个引导部分。引导部分与装配槽相对，并被接收在装配槽中。基板与至少一个发光二极管电连接。衬底板耦合到散热器。散热开口允许空气循环以去除由发光二极管产生的热量。此外，散热口形成为具有小于3mm的宽度W，并且散热器布置成与罩的圆周表面间隔大于6mm的距离。

15. 发明授权

US08046106B2 Controlling method and system for saving energy of building 有权
标题翻译：建筑节能控制方法与系统
公开(公告)号：US08046106B2
公开(公告)日：2011-10-25
申请号：US12336519
申请日：2008-12-16
申请人： Kun-Cheng Tsai , Chung-Yu Wang , Jing-Tian Sung
发明人： Kun-Cheng Tsai , Chung-Yu Wang , Jing-Tian Sung
IPC分类号： G01M1/38 , G05B13/00 , G05B15/00 , G05D23/00 , F24D19/10 , F24F11/00 , G05D23/275
CPC分类号： G05B15/02 , H04L67/12
摘要： A controlling method and a controlling system for saving energy of a building are provided. In the present method, a user environment requirement is obtained first. Then, a plurality of cover ratios of a sunshade device on an opening of a building is defined, and according to an environment parameter and the user environment requirement, a total electricity consumption required by air conditioning equipment and by lighting equipment in the building corresponding to each of the cover ratios is calculated. Finally, a cover ratio that produces the minimum total electricity consumption is obtained, and the sunshade device, the air conditioning equipment and the lighting equipment are adjusted according to the obtained cover ratio, so as to make the building meet the user environment requirement and maintain a status of the minimum total energy consumption.
摘要翻译：提供了一种用于节省建筑物能量的控制方法和控制系统。在本方法中，首先获得用户环境要求。然后，定义建筑物开口处的遮阳装置的多个覆盖率，并且根据环境参数和用户环境要求，空调设备和对应于建筑物的建筑物中的照明设备所需的总用电量计算每个覆盖率。最后，获得最小总耗电量的覆盖率，并根据获得的覆盖率调整遮阳装置，空调设备和照明设备，使建筑物满足用户环境要求并维护最低总能耗的状态。

16. 发明授权

US07443010B2 Matrix form semiconductor package substrate having an electrode of serpentine shape 有权
标题翻译：矩阵形式具有蛇形形状的电极的半导体封装基板
公开(公告)号：US07443010B2
公开(公告)日：2008-10-28
申请号：US09827106
申请日：2001-04-05
申请人： Pei-Haw Tsao , Chender Huang , Chung-Yu Wang
发明人： Pei-Haw Tsao , Chender Huang , Chung-Yu Wang
IPC分类号： H01L23/544 , H01L23/52 , H01L23/48
CPC分类号： H01L21/4846 , H01L23/49838 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/05647 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/00015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H05K3/0052 , H05K3/242 , H05K2201/09263 , H01L2224/85 , H01L2224/83 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A matrix form semiconductor package substrate that has an electrode situated in-between a plurality of IC package substrates for providing electrical communication to conductive pads on the substrate is provided. The matrix form semiconductor package substrate includes a plurality of IC package substrates that are integrally formed on a strip in a matrix pattern that has a boundary between each two of the plurality of IC package substrates. Each of the plurality of IC package substrates has a multiplicity of conductive pad traces and an electrode, or a plating bar, formed in a serpentine configuration along the boundary for providing electrical communication to the multiplicity of conductive pads.
摘要翻译：提供一种矩阵形式的半导体封装基板，其具有位于多个IC封装基板之间的电极，用于提供与基板上的导电焊盘的电连通。矩阵形式的半导体封装基板包括多个IC封装基板，其一体地形成在具有在所述多个IC封装基板中的每一个之间的边界的矩阵图案中的条带上。多个IC封装基板中的每一个具有多个导电焊盘迹线和沿边界形成为蛇形结构的电极或电镀条，用于提供与多个导电焊盘的电连通。

17. 发明申请

US20080174002A1 Stress relieving layer for flip chip packaging 有权
标题翻译：用于倒装芯片封装的应力消除层
公开(公告)号：US20080174002A1
公开(公告)日：2008-07-24
申请号：US11655844
申请日：2007-01-22
申请人： Chen-Shien Chen , Kuo-Chin Chang , Szu-Wei Lu , Pei-Haw Tsao , Chung-Yu Wang , Han-Liang Tseng , Mirng-Ji Lii
发明人： Chen-Shien Chen , Kuo-Chin Chang , Szu-Wei Lu , Pei-Haw Tsao , Chung-Yu Wang , Han-Liang Tseng , Mirng-Ji Lii
IPC分类号： H01L23/488 , H01L21/00
CPC分类号： H01L23/49816 , H01L21/4853 , H01L23/49827 , H01L24/02 , H01L24/11 , H01L24/16 , H01L2224/02319 , H01L2224/02321 , H01L2224/0401 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/351 , H01L2924/00
摘要： A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate. A plurality of solder balls is formed and mounted to the second surface of the second substrate. A third substrate is mounted to the solder balls.
摘要翻译：提供一种制造半导体封装的方法。在一个实施例中，提供其上具有多个暴露的导电层的半导体芯片。提供具有第一表面和第二表面的第一基底，所述第一表面在其下具有多个暴露的通孔塞。半导体芯片被接合到第一基板，其中多个暴露的导体层被对准并与暴露的通孔塞的表面接触。然后去除第一基板的第二表面的一部分以暴露多个通孔塞的相对端。在多个通孔塞的相对端的表面上形成多个UBM层。多个焊料凸起形成并安装在UBM层上。提供具有第一表面和第二表面的第二基底，焊料凸块安装到第二基底的第一表面。多个焊球形成并安装在第二基板的第二表面上。第三衬底安装到焊球。

18. 发明申请

US20080142994A1 Contact Pad And Bump Pad Arrangement for High-Lead Or Lead-Free Bumps 审中-公开
标题翻译：用于高铅或无铅冲击的接触垫和凸块安排
公开(公告)号：US20080142994A1
公开(公告)日：2008-06-19
申请号：US12036928
申请日：2008-02-25
申请人： Szu Wei Lu , Hsin-Hui Lee , Chung Yu Wang , Mirng-Ji Lii
发明人： Szu Wei Lu , Hsin-Hui Lee , Chung Yu Wang , Mirng-Ji Lii
IPC分类号： H01L23/52
CPC分类号： H01L24/10 , H01L23/3114 , H01L23/49816 , H01L24/13 , H01L2224/05124 , H01L2224/05147 , H01L2224/05559 , H01L2224/05571 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/13 , H01L2224/13099 , H01L2924/00011 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2924/00014 , H01L2924/00012 , H01L2224/81805 , H01L2924/013
摘要： A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with the first conductive pad, the first interface having a first linear dimension; the bump has a second interface with the second conductive pad, the second interface having a second linear dimension; and wherein the ratio of the first linear dimension and the second linear dimension is between about 0.7 and about 1.7.
摘要翻译：半导体封装组件包括半导体衬底上的第一导电焊盘; 封装衬底上的第二导电焊盘; 物理耦合在所述第一导电焊盘和所述第二导电焊盘之间的突起，其中所述突起基本上是无铅或高含铅的; 所述凸块具有与所述第一导电焊盘的第一界面，所述第一界面具有第一线性尺寸; 所述凸块具有与所述第二导电焊盘的第二接口，所述第二接口具有第二线性尺寸; 并且其中所述第一线性尺寸和所述第二线性尺寸的比率在约0.7和约1.7之间。

19. 发明授权

US06787926B2 Wire stitch bond on an integrated circuit bond pad and method of making the same 有权
标题翻译：集成电路接合焊盘上的线迹接合及其制造方法
公开(公告)号：US06787926B2
公开(公告)日：2004-09-07
申请号：US09947064
申请日：2001-09-05
申请人： Chih-Chiang Chen , Pei-Haw Tsao , Chung-Yu Wang
发明人： Chih-Chiang Chen , Pei-Haw Tsao , Chung-Yu Wang
IPC分类号： H01L2348
CPC分类号： H01L24/85 , H01L23/3128 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/05644 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48472 , H01L2224/48475 , H01L2224/48479 , H01L2224/48499 , H01L2224/48644 , H01L2224/48699 , H01L2224/4945 , H01L2224/73265 , H01L2224/78301 , H01L2224/85051 , H01L2224/85181 , H01L2224/85186 , H01L2224/85191 , H01L2224/85205 , H01L2224/85986 , H01L2225/06506 , H01L2225/0651 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2224/48744 , H01L2924/00012 , H01L2924/00015 , H01L2224/4554
摘要： A microelectronic assembly, and method of making the same, including a wire stitch bonded on an electroplated gold bump or electroless nickel/gold bump on a bond pad of an integrated circuit chip. The electroplated gold bump or electroless nickel/gold bump provides a relatively flat upper surface which is excellent for making a wire stitch bond thereto. The microelectronic assembly may include a multiple integrated circuit chip stack attached to a substrate such as a ball grid array. The electroplated gold bumps or electroless nickel/gold bumps may be formed on all of the integrated circuit chips and wire stitch bonds formed on the electroplated gold bumps or electroless nickel/gold bumps thereby connecting the integrated circuit chips to each other or to an underlying ball grid array.
摘要翻译：微电子组件及其制造方法，包括结合在集成电路芯片的焊盘上的电镀金凸块或化学镀镍/金凸块上的线迹。电镀金凸块或化学镀镍/金凸块提供相对平坦的上表面，其对于与其线接合而言是极好的。微电子组件可以包括附接到诸如球栅阵列的衬底的多个集成电路芯片堆叠。可以在形成在电镀金凸块或无电镍/金凸块上的所有集成电路芯片和线缝合上形成电镀金凸块或无电镀镍/金凸块，从而将集成电路芯片彼此连接或连接到下面的球网格阵列。

20. 发明授权

US08816495B2 Structures and formation methods of packages with heat sinks 有权
标题翻译：具有散热片的封装的结构和形成方法
公开(公告)号：US08816495B2
公开(公告)日：2014-08-26
申请号：US13398672
申请日：2012-02-16
申请人： Chung Yu Wang , Shih-Yi Syu , Jing-Cheng Lin
发明人： Chung Yu Wang , Shih-Yi Syu , Jing-Cheng Lin
IPC分类号： H01L23/34
CPC分类号： H01L23/433 , H01L21/563 , H01L23/147 , H01L23/367 , H01L23/49811 , H01L23/49827 , H01L24/97 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/181 , H01L2924/00
摘要： A device includes a package component, and a die over and bonded to the package component. The die includes a substrate. A heat sink is disposed over and bonded to a back surface of the substrate through direct bonding.
摘要翻译：一种装置包括一个封装部件和一个模具，并结合到封装部件上。芯片包括基板。散热器通过直接接合设置在基板的背面上并结合到基板的背面。

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