专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08101456B2 Method to reduce a via area in a phase change memory cell 有权
标题翻译：降低相变存储单元中的通孔面积的方法
公开(公告)号：US08101456B2
公开(公告)日：2012-01-24
申请号：US12243759
申请日：2008-10-01
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Yu Zhu
IPC分类号： H01L21/00
CPC分类号： H01L45/144 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/1683
摘要： A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer.
摘要翻译：存储单元结构和形成这种结构的方法。该方法部分地包括在底部电极的中心上形成氧化层内的通孔。该方法包括沿通孔的侧壁沉积通孔间隔物并氧化通孔间隔物。通孔间隔件由具有至少一个半的起珠床比的材料组成，并且当被氧化时是绝缘体。在氧化期间通孔间隔物的膨胀减小了通孔面积。或者，该方法部分地包括在底部电极的中心之上在第一层内形成通孔。第一层具有至少一个半的Pilling-Bedworth比，并且当被氧化时是绝缘体。该方法还包括在第一层中氧化通孔的侧壁的至少一部分。

12. 发明申请

US20110275209A1 VERTICAL FIELD EFFECT TRANSISTOR ARRAYS AND METHODS FOR FABRICATION THEREOF 有权
标题翻译：垂直场效应晶体管阵列及其制造方法
公开(公告)号：US20110275209A1
公开(公告)日：2011-11-10
申请号：US13185055
申请日：2011-07-18
申请人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L21/28
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译：垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。或者，阵列可以包括具有不同线宽的半导体柱，任选地在上述线宽和间隔距离限制的上下文中。用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。

13. 发明授权

US07981748B2 Method for fabricating a vertical field effect transistor array comprising a plurality of semiconductor pillars 有权
标题翻译：一种制造包括多个半导体柱的垂直场效应晶体管阵列的方法
公开(公告)号：US07981748B2
公开(公告)日：2011-07-19
申请号：US12541495
申请日：2009-08-14
申请人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L21/308
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译：垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。或者，阵列可以包括具有不同线宽的半导体柱，任选地在上述线宽和间隔距离限制的上下文中。用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。

14. 发明授权

US07944740B2 Multi-level cell programming of PCM by varying the reset amplitude 失效
标题翻译：通过改变复位幅度对PCM进行多级单元编程
公开(公告)号：US07944740B2
公开(公告)日：2011-05-17
申请号：US12564904
申请日：2009-09-22
申请人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
发明人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
摘要： A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.
摘要翻译：相变存储器件及其编程方法。该方法包括确定用于相变存储器件的特征最低的SET电流和相应的SET电阻。该方法包括确定用于相变存储器件的特征化的RESET电流斜率。该方法还包括基于所表征的最低SET电流和表征的RESET电流斜率来计算RESET脉冲的第一电流幅度。该方法包括将RESET脉冲施加到相变存储器件中的目标存储单元并测量目标存储单元的电阻。如果所测量的电阻远小于目标电阻，该方法还包括应用一个或多个附加的RESET脉冲。在本发明的一个实施例中，一个或多个附加的RESET脉冲的电流幅度大于先前施加的RESET脉冲。

15. 发明授权

US07943919B2 Integrated circuit with upstanding stylus 有权
标题翻译：集成电路与直立手写笔
公开(公告)号：US07943919B2
公开(公告)日：2011-05-17
申请号：US10732579
申请日：2003-12-10
申请人： David V. Horak , Chung H. Lam
发明人： David V. Horak , Chung H. Lam
IPC分类号： H01L45/00
CPC分类号： H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： A stylus, an integrated circuit (IC) and method of forming the IC. The stylus extends upward from its apex and has a substantially circular cross section that decreases in diameter upward from the apex. The stylus is formed in a mold that may be formed in an orifice in a dielectric layer between wiring layers. The mold may include multiple concentric layers. For a more pronounced, non-linear stylus taper, each layer may be thinner than its next adjacent outer concentric layer.
摘要翻译：触笔，集成电路（IC）和IC的形成方法。触针从其顶点向上延伸并且具有从顶点向上直径减小的大致圆形横截面。触针形成在可以形成在布线层之间的电介质层中的孔中的模具中。模具可以包括多个同心层。对于更明显的非线性触针锥形，每个层可以比其下一个相邻的外部同心层更薄。

16. 发明申请

US20110108960A1 SUB-LITHOGRAPHIC PRINTING METHOD 失效
标题翻译：分层印刷方法
公开(公告)号：US20110108960A1
公开(公告)日：2011-05-12
申请号：US13006403
申请日：2011-01-13
申请人： Chung H. Lam , Hemantha K. Wickramasinghe
发明人： Chung H. Lam , Hemantha K. Wickramasinghe
IPC分类号： H01L21/02 , H01L29/06
CPC分类号： H01L21/0337
摘要： A trench structure and an integrated circuit comprising sub-lithographic trench structures in a substrate. In one embodiment the trench structure is created by forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size.
摘要翻译：沟槽结构和集成电路，其包括衬底中的次光刻沟槽结构。在一个实施例中，沟槽结构是通过用光刻掩膜形成一组沟槽而形成的，并且用一组间隔块块填充该组沟槽，该组间隔块包括彼此分离地可拆卸的两个交替间隔物材料。在一个实施例中，形成的沟槽结构是光刻掩模的特征尺寸的厚度的十分之一。沟槽结构的尺寸取决于用于形成一组步进间隔块的间隔材料层的厚度和数量。间隔材料层的数量为n / 2，每个间隔材料层的厚度为光刻掩模的特征尺寸的十分之一。

17. 发明申请

US20110049460A1 SINGLE MASK ADDER PHASE CHANGE MEMORY ELEMENT 有权
标题翻译：单面罩相机更换记忆元件
公开(公告)号：US20110049460A1
公开(公告)日：2011-03-03
申请号：US12549997
申请日：2009-08-28
申请人： Matthew J. Breitwisch , Chandrasekharan Kothandaraman , Chung H. Lam
发明人： Matthew J. Breitwisch , Chandrasekharan Kothandaraman , Chung H. Lam
IPC分类号： H01L45/00 , H01L21/06 , H01L21/3105
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： A method of fabricating a phase change memory element within a semiconductor structure includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region at a same layer within the semiconductor structure, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material.
摘要翻译：在半导体结构内制造相变存储元件的方法包括蚀刻到底部电极的上表面的开口，该开口由等于半导体结构内同一层的金属区域的高度的高度形成，在开口内沉积相变材料，使开关内的相变材料凹陷，并在凹陷相变材料上形成顶部电极。

18. 发明授权

US07894272B2 Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition 有权
标题翻译：利用测量时间延迟作为电平定义的特征参数的多电平存储单元
公开(公告)号：US07894272B2
公开(公告)日：2011-02-22
申请号：US12698141
申请日：2010-02-02
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C16/06
CPC分类号： G11C13/0061 , G11C11/5628 , G11C11/565 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C16/32 , G11C2013/0054
摘要： A computer program product for operating a memory cell and memory array. The computer program product of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.
摘要翻译：一种用于操作存储器单元和存储器阵列的计算机程序产品。存储单元操作的计算机程序产品需要接收读取存储在存储单元中的二进制值的请求。预充电操作将由存储单元形成的电子电路中的位线电容器预先充电到预充电电压。然后激活电子电路中的字线。放电操作通过电子电路中的所述存储单元将位线电容器放电到字线。此外，当字线被激活时，电子放电时间测量开始。当位线中的电压电平低于预定义的参考电压时，停止电子放电时间测量。确定操作根据测量的电子放电时间确定二进制值。

19. 发明授权

US07881089B2 Coding techniques for improving the sense margin in content addressable memories 有权
标题翻译：用于改善内容可寻址存储器中的检测边缘的编码技术
公开(公告)号：US07881089B2
公开(公告)日：2011-02-01
申请号：US12392049
申请日：2009-02-24
申请人： Michele M. Franceschini , Chung H. Lam , Luis A. Lastras , Bipin Rajendran
发明人： Michele M. Franceschini , Chung H. Lam , Luis A. Lastras , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G11C7/1006 , G11C13/0004 , G11C15/02 , G11C15/046
摘要： A content addressable memory using encoded data words and search words, and techniques for operating such device. In one embodiment, the data word is transformed into a code word guaranteeing a mismatch of at least two code word bits of different binary values during the memory search operation when the data word does not match a search word. In another embodiment, the search word is transformed into a search code such that the Hamming distance between the code word and the search code is greater than a given threshold when there is a mismatch of at least one bit between the data word and the search word.
摘要翻译：使用编码数据字和搜索词的内容可寻址存储器，以及用于操作这样的设备的技术。在一个实施例中，当数据字与搜索词不匹配时，数据字被转换成保证在存储器搜索操作期间不同二进制值的至少两个码字位的失配的码字。在另一个实施例中，搜索词被变换成搜索码，使得当数据字和搜索词之间存在至少一个比特的不匹配时，码字和搜索码之间的汉明距离大于给定阈值。

20. 发明申请

US20100265748A1 HIGH DENSITY TERNARY CONTENT ADDRESSABLE MEMORY 有权
标题翻译：高密度内容可寻址存储器
公开(公告)号：US20100265748A1
公开(公告)日：2010-10-21
申请号：US12427484
申请日：2009-04-21
申请人： Chung H. Lam , Bipin Rajendran
发明人： Chung H. Lam , Bipin Rajendran
IPC分类号： G11C15/00 , G11C11/00 , G11C11/56
CPC分类号： G11C15/046 , G11C11/5678 , G11C13/0004
摘要： A content addressable memory device with a plurality of memory cells storing data words. Each data bit in the data words is set to one of three values of a first binary value, a second binary value, and a don't care value. An aspect of the content addressable memory device is the use of a single memory element and an access device in the memory cells. The memory cells are arranged such that each memory cell is electrically coupled to a single bit line, a single match line, and a single word line. The memory elements in the memory cells store low resistance states if the data bit value is the first binary value, high resistance states if the data bit value is the second binary value, and very high resistance states if the data bit value is the don't care value.
摘要翻译：一种具有存储数据字的多个存储器单元的内容可寻址存储器件。数据字中的每个数据位被设置为第一二进制值，第二二进制值和不关心值的三个值之一。内容可寻址存储器件的一个方面是在存储器单元中使用单个存储器元件和存取器件。存储器单元被布置成使得每个存储器单元电耦合到单个位线，单个匹配线和单个字线。如果数据位值是第一个二进制值，则存储器单元中的存储元件存储低电阻状态，如果数据位值是第二个二进制值则为高电阻状态，如果数据位值为“ 关心价值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式