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11. 发明申请

US20130228875A1 Apparatus and Method for FinFETs 有权
公开(公告)号：US20130228875A1
公开(公告)日：2013-09-05
申请号：US13410073
申请日：2012-03-01
申请人： Yi-Jing Lee , You-Ru Lin , Cheng-Tien Wan , Cheng-Hsien Wu , Chih-Hsin Ko
发明人： Yi-Jing Lee , You-Ru Lin , Cheng-Tien Wan , Cheng-Hsien Wu , Chih-Hsin Ko
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/02532 , H01L21/0262 , H01L21/02631 , H01L21/02634 , H01L21/30625 , H01L21/3065 , H01L21/76224 , H01L27/0886 , H01L29/7853
摘要： A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.

12. 发明申请

US20130168771A1 Method of Forming CMOS FinFET Device 有权
标题翻译： CMOS FinFET器件的形成方法
公开(公告)号：US20130168771A1
公开(公告)日：2013-07-04
申请号：US13340937
申请日：2011-12-30
申请人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L27/12 , H01L21/84 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/1211 , H01L21/823821 , H01L21/8258 , H01L21/845 , H01L29/1054 , H01L29/267
摘要： A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin.
摘要翻译：公开了一种用于制造CMOS FinFET器件的CMOS FinFET器件和方法。示例性的CMOS FinFET器件包括包括第一区域和第二区域的衬底。 CMOS FinFET还包括布置在衬底上的翅片结构，其包括在第一区域中的第一鳍片和在第二区域中的第二鳍片。 CMOS FinFET还包括第一鳍片的第一部分，其包括与衬底相同的材料的材料，以及第一鳍片的第二部分，其包括沉积在第一鳍片的第一部分上的III-V半导体材料。 CMOS FinFET还包括第二鳍片的第一部分，其包括与衬底相同的材料，第二鳍片的第二部分包括沉积在第二鳍片的第一部分上的锗（Ge）材料。

13. 发明授权

US08455860B2 Reducing source/drain resistance of III-V based transistors 有权
标题翻译：降低III-V晶体管的源极/漏极电阻
公开(公告)号：US08455860B2
公开(公告)日：2013-06-04
申请号：US12616073
申请日：2009-11-10
申请人： Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L29/12
CPC分类号： H01L29/78 , H01L21/22 , H01L29/41775 , H01L29/66462 , H01L29/7783
摘要： An integrated circuit structure includes a substrate; a channel layer over the substrate, wherein the channel layer is formed of a first III-V compound semiconductor material; a highly doped semiconductor layer over the channel layer; a gate dielectric penetrating through and contacting a sidewall of the highly doped semiconductor layer; and a gate electrode on a bottom portion of the gate dielectric. The gate dielectric includes a sidewall portion on a sidewall of the gate electrode.
摘要翻译：集成电路结构包括：基板; 在所述衬底上的沟道层，其中所述沟道层由第一III-V族化合物半导体材料形成; 在沟道层上的高掺杂半导体层; 栅介质穿透并接触高掺杂半导体层的侧壁; 以及在栅极电介质的底部上的栅电极。栅极电介质包括在栅电极的侧壁上的侧壁部分。

14. 发明申请

US20110272739A1 METHOD FOR FABRICATING A STRAINED STRUCTURE 有权
标题翻译：制造应变结构的方法
公开(公告)号：US20110272739A1
公开(公告)日：2011-11-10
申请号：US12775006
申请日：2010-05-06
申请人： Tsung-Lin LEE , Chih-Hao CHANG , Chih-Hsin KO , Feng YUAN , Jeff J. XU
发明人： Tsung-Lin LEE , Chih-Hao CHANG , Chih-Hsin KO , Feng YUAN , Jeff J. XU
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L21/30604 , H01L21/31 , H01L21/31116 , H01L21/76 , H01L29/0653 , H01L29/0847 , H01L29/0856 , H01L29/0873 , H01L29/1608 , H01L29/165 , H01L29/6653 , H01L29/66553 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.
摘要翻译：一种用于衬底上的场效应晶体管的结构，其包括栅极堆叠，隔离结构以及位于栅叠层和隔离结构之间的衬底顶表面下方的源极/漏极（S / D）凹槽。该凹腔具有下部和上部。下部具有第一应变层和第一介电膜。第一应变层设置在隔离结构和第一介电膜之间。第一电介质膜的厚度小于第一应变层的厚度。上部具有覆盖在第一应变层和第一介电膜上的第二应变层。

15. 发明申请

US20100301390A1 Gradient Ternary or Quaternary Multiple-Gate Transistor 有权
标题翻译：梯度三元或四元多栅极晶体管
公开(公告)号：US20100301390A1
公开(公告)日：2010-12-02
申请号：US12616068
申请日：2009-11-10
申请人： Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L31/0304
CPC分类号： H01L29/7851 , H01L29/66795
摘要： An integrated circuit structure includes a semiconductor substrate; insulation regions over the semiconductor substrate; and an epitaxy region over the semiconductor substrate and having at least a portion in a space between the insulation regions. The epitaxy region includes a III-V compound semiconductor material. The epitaxy region also includes a lower portion and an upper portion over the lower portion. The lower portion and the semiconductor substrate have a first lattice mismatch. The upper portion and the semiconductor substrate have a second lattice mismatch different from the first lattice mismatch.
摘要翻译：集成电路结构包括半导体衬底; 半导体衬底上的绝缘区域; 以及半导体衬底上的外延区域，并且在绝缘区域之间具有空间中的至少一部分。该外延区域包括III-V族化合物半导体材料。外延区域还包括下部和下部上的上部。下部和半导体衬底具有第一晶格失配。上部和半导体衬底具有与第一晶格失配不同的第二晶格失配。

16. 发明申请

US20100252862A1 Source/Drain Engineering of Devices with High-Mobility Channels 有权
标题翻译：高移动通道设备的源/漏工程
公开(公告)号：US20100252862A1
公开(公告)日：2010-10-07
申请号：US12615996
申请日：2009-11-10
申请人： Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L29/772
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/66651 , H01L29/66795 , H01L29/7848
摘要： An integrated circuit structure includes a substrate, and a channel over the substrate. The channel includes a first III-V compound semiconductor material formed of group III and group V elements. A gate structure is over the channel. A source/drain region is adjacent the channel and includes a group-IV region formed of a doped group-IV semiconductor material selected from the group consisting essentially of silicon, germanium, and combinations thereof.
摘要翻译：集成电路结构包括衬底和衬底上的沟道。该通道包括由III族和V族元素形成的第一III-V族化合物半导体材料。门结构在通道之上。源极/漏极区域与沟道相邻并且包括由掺杂的基团IV半导体材料形成的IV族区域，该掺杂基团IV半导体材料主要由硅，锗及其组合组成。

17. 发明申请

US20100213512A1 High-Mobility Channel Devices on Dislocation-Blocking Layers 有权
标题翻译：位移阻挡层上的高移动通道设备
公开(公告)号：US20100213512A1
公开(公告)日：2010-08-26
申请号：US12618004
申请日：2009-11-13
申请人： Chih-Hsin Ko
发明人： Chih-Hsin Ko
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L21/823807 , H01L21/8258 , H01L29/7783 , H01L29/7833
摘要： A method of forming an integrated circuit structure includes forming a first recess in the semiconductor substrate; and forming a dislocation-blocking layer in the first recess. The dislocation-blocking layer includes a semiconductor material. Shallow trench isolation (STI) regions are formed, wherein inner portions of the STI regions are directly over portions of the dislocation-blocking layer, and wherein inner sidewalls of the STI regions contact the dislocation-blocking layer. A second recess is formed by removing a portion of the dislocation-blocking layer between two of the inner sidewalls of the STI regions, with the two inner sidewalls facing each other. A semiconductor region is epitaxially grown in the second recess.
摘要翻译：形成集成电路结构的方法包括在半导体衬底中形成第一凹槽; 以及在所述第一凹部中形成位错阻挡层。位错阻挡层包括半导体材料。形成浅沟槽隔离（STI）区域，其中STI区域的内部部分直接位于位错阻挡层的部分上，并且其中STI区域的内侧壁与位错阻挡层接触。通过在STI区域的两个内侧壁之间移除一部分位错阻挡层而形成第二凹槽，两个内侧壁彼此面对。在第二凹部中外延生长半导体区域。

18. 发明申请

US20090140351A1 MOS Devices Having Elevated Source/Drain Regions 审中-公开
标题翻译： MOS器件具有升高的源/漏区域
公开(公告)号：US20090140351A1
公开(公告)日：2009-06-04
申请号：US11948823
申请日：2007-11-30
申请人： Hong-Nien Lin , Chih-Hsin Ko , Hung-Wei Chen , Wen-Chin Lee
发明人： Hong-Nien Lin , Chih-Hsin Ko , Hung-Wei Chen , Wen-Chin Lee
IPC分类号： H01L29/78
CPC分类号： H01L29/6656 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66537 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming a slim spacer on sidewalls of the gate dielectric and the gate electrode; forming a silicon carbon (SiC) region adjacent the slim spacer; forming a deep source/drain region comprising at least a portion of the silicon carbon region; blanket forming a metal layer, wherein a first interface between the metal layer and the deep source/drain is higher than a second interface between the gate dielectric and the semiconductor substrate; and annealing the semiconductor device to form a silicide region. Preferably, a horizontal spacing between an inner edge of the silicide region and a respective edge of the gate electrode is preferably less than about 150 Å.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅极电介质和所述栅电极的侧壁上形成细长间隔物; 形成邻近细长间隔物的硅碳（SiC）区域; 形成包含所述硅碳区域的至少一部分的深源极/漏极区域; 毯形成金属层，其中金属层和深源极/漏极之间的第一界面高于栅极电介质和半导体衬底之间的第二界面; 并对半导体器件进行退火以形成硅化物区域。优选地，硅化物区域的内边缘和栅电极的相应边缘之间的水平间隔优选小于约150埃。

19. 发明申请

US20090117695A1 BiCMOS Performance Enhancement by Mechanical Uniaxial Strain and Methods of Manufacture 有权
标题翻译：机械单轴应变的BiCMOS性能提升及制造方法
公开(公告)号：US20090117695A1
公开(公告)日：2009-05-07
申请号：US12260674
申请日：2008-10-29
申请人： Chih-Hsin Ko , Tzu-Juei Wang , Hung-Wei Chen , Chung-Hu Ke , Wen-Chin Lee
发明人： Chih-Hsin Ko , Tzu-Juei Wang , Hung-Wei Chen , Chung-Hu Ke , Wen-Chin Lee
IPC分类号： H01L21/8249
CPC分类号： H01L21/8249 , H01L21/823807 , H01L27/0623 , H01L29/7843
摘要： A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.
摘要翻译：提供了通过机械单轴应变增强性能的BiCMOS器件。本发明的第一实施例包括形成在衬底的不同区域上的NMOS晶体管，PMOS晶体管和双极晶体管。具有拉伸应力的第一接触蚀刻停止层形成在NMOS晶体管上，并且在PMOS晶体管和双极晶体管上形成具有压应力的第二接触蚀刻停止层，从而允许每个器件的增强。除了应力接触蚀刻停止层之外，另一实施例还包括PMOS晶体管和NMOS晶体管中的应变通道区域以及BJT中的应变基极。

20. 发明申请

US20080145982A1 ISOLATION SPACER FOR THIN SOI DEVICES 有权
公开(公告)号：US20080145982A1
公开(公告)日：2008-06-19
申请号：US12036616
申请日：2008-02-25
申请人： Chih-Hsin KO , Wen-Chin Lee , Yee-Chia Yeo , Chung-Hu Ke
发明人： Chih-Hsin KO , Wen-Chin Lee , Yee-Chia Yeo , Chung-Hu Ke
IPC分类号： H01L21/00 , H01L21/3205
CPC分类号： H01L29/66772 , H01L27/1203 , H01L29/78618 , Y10S257/90
摘要： A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.

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