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11. 发明授权

US07725751B2 Termination techniques for bus interfaces 有权
标题翻译：总线接口终端技术
公开(公告)号：US07725751B2
公开(公告)日：2010-05-25
申请号：US11618496
申请日：2006-12-29
申请人： Blaise Fanning , Binta M. Patel
发明人： Blaise Fanning , Binta M. Patel
IPC分类号： G06F1/00
CPC分类号： G06F1/3253 , G06F1/3228 , Y02D10/151 , Y02D50/20
摘要： Techniques involving the transfer of signals across interconnection media are disclosed. For instance, an apparatus may include an apparatus having an interconnection medium, a first device that may drive the interconnection medium, and a second device. The second device may include a pull-up resistor that is selectively coupled between the interconnection medium and a power source. For instance, the second device may disconnect a power source from the interconnection medium when the first device is in a power saving operational state. Otherwise, the pull-up resistance is coupled between the power source and the interconnection medium.
摘要翻译：公开了涉及通过互连介质传送信号的技术。例如，设备可以包括具有互连介质的设备，可以驱动互连介质的第一设备和第二设备。第二装置可以包括上拉电阻器，其被选择性地耦合在互连介质和电源之间。例如，当第一设备处于节电操作状态时，第二设备可以断开电源与互连介质的连接。否则，上拉电阻耦合在电源和互连介质之间。

12. 发明申请

US20090193164A1 General Input/Output Architecture, Protocol and Related Methods to Implement Flow Control 有权
标题翻译：一般输入/输出架构，协议和相关方法来实现流量控制
公开(公告)号：US20090193164A1
公开(公告)日：2009-07-30
申请号：US12395497
申请日：2009-02-27
申请人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
发明人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
IPC分类号： G06F13/14 , G06F13/00
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method for an enhanced general input/output communication architecture includes initializing a flow control mechanism within an general input/output (GIO) interface associated with a virtual channel upon initialization of the virtual channel, and tracking receive buffer availability in a remote GIO interface coupled with the GIO interface by the virtual channel by monitoring an indication associated with an amount of content transmitted from the GIO interface to the remote GIO interface.
摘要翻译：提出了一种增强的通用输入/输出通信架构，协议和相关方法。在一个实施例中，用于增强的一般输入/输出通信架构的方法包括：初始化虚拟通道初始化时初始化与虚拟通道相关联的通用输入/输出（GIO）接口内的流控制机制，以及在虚拟通道初始化时跟踪接收缓冲区可用性通过监视与从GIO接口发送到远程GIO接口的内容量相关联的指示，通过虚拟通道与远程GIO接口耦合到GIO接口。

13. 发明申请

US20080162748A1 EFFICIENT POWER MANAGEMENT TECHNIQUES FOR COMPUTER SYSTEMS 审中-公开
标题翻译：计算机系统的高效电源管理技术
公开(公告)号：US20080162748A1
公开(公告)日：2008-07-03
申请号：US11618878
申请日：2006-12-31
申请人： Blaise Fanning
发明人： Blaise Fanning
IPC分类号： G06F5/00
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/14
摘要： Techniques involving power management techniques in computer systems are disclosed. For instance, an apparatus may include an input output queue (IOQ), an interface coupled to a processor, and a control module. The interface communicates with the processor regarding power states of the processor. The control module may initiate draining the IOQ upon a commencement of a power state transition for the processor. The control module allows the transition of the processor to continue during the draining of the IOQ. However, at a particular point in the transition, the control module may determine whether the IOQ is empty. If so, then the control module may allow the transition of the processor to continue. Otherwise, the control module may stop the transition of the processor until the IOQ is empty.
摘要翻译：公开了涉及计算机系统中的电力管理技术的技术。例如，设备可以包括输入输出队列（IOQ），耦合到处理器的接口和控制模块。接口与处理器通信处理器的电源状态。控制模块可以在处理器的功率状态转换开始时启动排出IOQ。控制模块允许处理器在IOQ排水期间继续进行。然而，在转换中的特定点处，控制模块可以确定IOQ是否为空。如果是这样，则控制模块可以允许处理器的转换继续。否则，控制模块可能会停止处理器的转换，直到IOQ为空。

14. 发明授权

US07353313B2 General input/output architecture, protocol and related methods to manage data integrity 有权
标题翻译：一般输入/输出架构，协议和相关方法来管理数据完整性
公开(公告)号：US07353313B2
公开(公告)日：2008-04-01
申请号：US11585648
申请日：2006-10-23
申请人： Eric R. Wehage , Jasmin Ajanovic , David Harriman , David M. Lee , Blaise Fanning , Buck Gremel , Ken Creta , Wayne Moore
发明人： Eric R. Wehage , Jasmin Ajanovic , David Harriman , David M. Lee , Blaise Fanning , Buck Gremel , Ken Creta , Wayne Moore
IPC分类号： G06F13/14
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： An enhanced general input/output (EGIO) communication architecture, protocol and related methods are presented. The elements of an EGIO architecture may include one or more of a root complex (e.g., implemented within a bridge), a switch, and end-points, each incorporating at least a subset of EGIO features to support EGIO communication between such elements.
摘要翻译：提出了一种增强的一般输入/输出（EGIO）通信架构，协议和相关方法。 EGIO架构的元件可以包括根复合体（例如，在桥内实现），交换机和终点中的一个或多个，每个结合至少一个EGIO特征的子集以支持这些元素之间的EGIO通信。

15. 发明申请

US20060143402A1 Mechanism for processing uncacheable streaming data 审中-公开
标题翻译：处理不可流水的数据流的机制
公开(公告)号：US20060143402A1
公开(公告)日：2006-06-29
申请号：US11021662
申请日：2004-12-23
申请人： Srinivas Chennupaty , Jack Doweck , Blaise Fanning , Prashant Sethi , Opher Kahn
发明人： Srinivas Chennupaty , Jack Doweck , Blaise Fanning , Prashant Sethi , Opher Kahn
IPC分类号： G06F13/00
CPC分类号： G06F12/0831 , G06F9/30043 , G06F9/30087 , G06F9/383 , G06F12/0888
摘要： In one embodiment, a buffer is presented. The buffer comprises a type designator to designate that the buffer is a streaming read buffer, and a plurality of use designators to indicate whether data within the buffer has been used. The data within the buffer is an uncacheable memory type, such as Uncacheable Speculative Write Combining (USWC) memory. Furthermore, in some embodiments, the buffer is allocated upon execution of a streaming read buffer instruction. In other embodiments, the data within the buffer can only be used once and cannot be cached elsewhere in the processor.
摘要翻译：在一个实施例中，呈现缓冲器。缓冲器包括用于指定缓冲器是流读取缓冲器的类型指示符，以及指示缓冲器内的数据是否已被使用的多个使用指示符。缓冲区中的数据是不可缓存的存储器类型，例如不可缓存的推测写入组合（USWC）存储器。此外，在一些实施例中，在执行流读取缓冲器指令时分配缓冲器。在其他实施例中，缓冲器内的数据只能使用一次，并且不能被缓存在处理器的其他地方。

16. 发明申请

US20060127059A1 Media player with high-resolution and low-resolution image frame buffers 审中-公开
标题翻译：具有高分辨率和低分辨率图像帧缓冲器的媒体播放器
公开(公告)号：US20060127059A1
公开(公告)日：2006-06-15
申请号：US11011573
申请日：2004-12-14
申请人： Blaise Fanning
发明人： Blaise Fanning
IPC分类号： H04N5/85
CPC分类号： H04N21/4621 , H04N19/423 , H04N19/59 , H04N19/89 , H04N21/23439 , H04N21/44004
摘要： According to some embodiments, a low-resolution buffer may be provided to store lower-resolution image frame information associated with first media content. A high-resolution buffer may also be provided to store higher-resolution image frame information also associated with the first media content. A playback device may then receive (i) the higher-resolution image frame information if the higher-resolution image frame information is available or (ii) the lower-resolution image frame information if the higher-resolution image frame information is not available.
摘要翻译：根据一些实施例，可以提供低分辨率缓冲器来存储与第一媒体内容相关联的较低分辨率图像帧信息。还可以提供高分辨率缓冲器来存储也与第一媒体内容相关联的更高分辨率的图像帧信息。如果较高分辨率图像帧信息可用，则再现设备可以接收（i）较高分辨率图像帧信息，或者如果较高分辨率图像帧信息不可用，则可以接收较低分辨率图像帧信息。

17. 发明申请

US20050259579A1 Bounding data transmission latency based upon link loading and arrangement 审中-公开
公开(公告)号：US20050259579A1
公开(公告)日：2005-11-24
申请号：US11132615
申请日：2005-05-18
申请人： Blaise Fanning
发明人： Blaise Fanning
IPC分类号： H04L1/24 , H04L12/26
CPC分类号： H04L1/24
摘要： A method, apparatus, system, and machine-readable medium to bound data transmission latency by transmitting error verification data at a point during a data transmission based upon loading of a channel for the data transmission is provided. Embodiments may comprise determining the loading of a communication channel and transmitting error verification data to a target device based upon the loading. More specifically, some embodiments transmit error verification data at intervals, variable intervals in some embodiments, to balance transmission latency against the bandwidth available from a communication medium.

18. 发明授权

US5315696A Graphics command processing method in a computer graphics system 失效
标题翻译：图形命令处理方法在计算机图形系统中
公开(公告)号：US5315696A
公开(公告)日：1994-05-24
申请号：US748352
申请日：1991-08-21
申请人： Colyn Case , Kim Meinerth , John Irwin , Blaise Fanning
发明人： Colyn Case , Kim Meinerth , John Irwin , Blaise Fanning
IPC分类号： G09G5/00 , G09G5/02 , G09G5/14 , G09G5/36 , G09G5/39 , G06F15/62
CPC分类号： G09G5/363 , G09G5/024 , G09G5/14 , G09G5/39 , G09G2360/127 , G09G5/006
摘要： In a computer graphics system, an address generator processes physical and virtual addresses using a common command set. A separate translator provides conversion from generated virtual addresses to physical addresses. The address generator formulates addresses as a function of distance from the origin of desired destination area in destination memory to the requested position in the destination area. A plurality of drawing graphics commands specify different raster drawing operations. A plurality of context graphics commands is used to define a desired context in which drawing graphics commands operate. The defined context includes destination location for resulting data, type and plane depth of graphics operations, foreground and/or background color of resulting data. Different parts of the context are changeable/redefinable independently of the other parts.
摘要翻译：在计算机图形系统中，地址生成器使用公共命令集处理物理和虚拟地址。单独的翻译器提供从生成的虚拟地址到物理地址的转换。地址生成器根据从目的地存储器中的期望目的地区域的原点到目的地区域中的请求位置的距离来形成地址。多个绘图图形命令指定不同的光栅绘图操作。使用多个上下文图形命令来定义绘图图形命令操作的所需上下文。定义的上下文包括结果数据的目标位置，图形操作的类型和平面深度，结果数据的前景和/或背景颜色。上下文的不同部分可以独立于其他部分进行变化/重新定义。

19. 发明授权

US09529708B2 Apparatus for configuring partitions within phase change memory of tablet computer with integrated memory controller emulating mass storage to storage driver based on request from software 有权
标题翻译：用于在具有集成存储器控制器的平板计算机的相变存储器内配置分区的装置，其基于来自软件的请求将存储驱动器模拟到存储驱动器
公开(公告)号：US09529708B2
公开(公告)日：2016-12-27
申请号：US13976362
申请日：2011-09-30
申请人： Leena K. Puthiyedath , Blaise Fanning , Toby Opferman , James B. Crossland
发明人： Leena K. Puthiyedath , Blaise Fanning , Toby Opferman , James B. Crossland
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08 , G06F12/06
CPC分类号： G06F3/0679 , G06F3/061 , G06F3/0631 , G06F3/0643 , G06F3/0644 , G06F12/00 , G06F12/0238 , G06F12/0638 , G06F12/08 , G06F12/0804 , G06F12/0866 , G06F2212/1004 , G06F2212/1056 , G06F2212/2024 , G06F2212/214 , G06F2212/251 , G06F2212/7201
摘要： A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.
摘要翻译：在计算机系统中使用非易失性随机存取存储器（NVRAM）来在平台存储层级中执行多个角色，特别是替换可由I / O访问的传统大容量存储。计算机系统包括执行软件的处理器和耦合到处理器的存储器。存储器的至少一部分包括可由处理器进行字节可重写和字节可擦除的非易失性随机存取存储器（NVRAM）。该系统还包括耦合到NVRAM的存储器控制器，以响应于来自软件的访问大容量存储器的请求来执行存储器访问操作以访问NVRAM。

20. 发明申请

US20140258492A1 AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE 审中-公开
标题翻译：在边界接口中聚合完成信息
公开(公告)号：US20140258492A1
公开(公告)日：2014-09-11
申请号：US14209207
申请日：2014-03-13
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Mohan K. Nair , Joseph Murray , Rohit R. Verma , Gary J. Lavelle , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Mohan K. Nair , Joseph Murray , Rohit R. Verma , Gary J. Lavelle , Robert P. Adler
IPC分类号： H04L12/761
CPC分类号： G06F13/364 , G06F13/385 , G06F13/4265 , G06F15/7807 , G06F15/7825 , G06F2213/0038 , H04L12/28 , H04L12/54 , H04L45/00 , H04L45/16
摘要： In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从耦合到路由器的第一端点在路由器中接收请求的方法，其中该请求用于聚合完成。反过来，路由器可以将请求转发到多个目标代理，从每个目标代理接收响应，并将响应合并到聚合完成中。然后，路由器可以将聚合完成发送到第一个端点。描述和要求保护其他实施例。

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