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11. 发明授权

US06748484B1 Match resolution circuit for an associative memory 失效
标题翻译：匹配分辨率电路用于关联存储器
公开(公告)号：US06748484B1
公开(公告)日：2004-06-08
申请号：US09637131
申请日：2000-08-10
申请人： Alex E. Henderson , Walter E. Croft , Raymond M. Chu , Vishal Sarin
发明人： Alex E. Henderson , Walter E. Croft , Raymond M. Chu , Vishal Sarin
IPC分类号： G06F1200
CPC分类号： G11C15/00 , G11C15/04
摘要： A system and method for determining a best match from a plurality of matches received in response to a search input for an associative memory includes a priority field associated with each data item stored in the associative memory. The priority field corresponds to criteria that is used to order the priority of the data items in the associative memory. A match resolution circuit is coupled to receive match signals from an associative memory, such as a CAM, and the priority fields of the matching data items. The match resolution structure compares the priority fields of the matching data items to determine which data item has the highest priority. The match resolution structure indicates the data item with the highest priority in the priority field as the best match of the associative memory for the particular search input.
摘要翻译：用于响应于关联存储器的搜索输入而接收的多个匹配来确定最佳匹配的系统和方法包括与存储在关联存储器中的每个数据项相关联的优先级字段。优先级字段对应于用于对关联存储器中的数据项的优先级进行排序的标准。匹配分辨率电路被耦合以从诸如CAM的关联存储器和匹配数据项的优先级字段接收匹配信号。匹配分辨率结构比较匹配数据项的优先级字段以确定哪个数据项具有最高优先级。匹配分辨率结构指示优先级字段中具有最高优先级的数据项作为特定搜索输入的关联存储器的最佳匹配。

12. 发明授权

US06175514B1 Content addressable memory device 失效
标题翻译：内容可寻址存储设备
公开(公告)号：US06175514B1
公开(公告)日：2001-01-16
申请号：US09384810
申请日：1999-08-27
申请人： Alex E. Henderson , Walter E. Croft
发明人： Alex E. Henderson , Walter E. Croft
IPC分类号： G11C1500
CPC分类号： G11C7/1075 , G11C15/00 , G11C15/04 , Y10S623/915
摘要： A content addressable memory device is provided which may include a novel CAM cell structure which reduces the total power dissipated by the CAM and improves the match time for the CAM. The novel CAM cell structure may include a CMOS implemented compare cell and a wide AND gate which combines the match decisions for each CAM cell into a match decision. The CAM cell structure may be implemented in a variety of different CAM devices, including dual port CAM devices, CAM devices with individual bit masking, event co-processors and database co-processors.
摘要翻译：提供了一种可内容寻址的存储器件，其可以包括一种新颖的CAM单元结构，其减少CAM消耗的总功率并改善CAM的匹配时间。该新颖的CAM单元结构可以包括CMOS实施的比较单元和宽的AND门，其将每个CAM单元的匹配决定组合成匹配决定。 CAM单元结构可以在各种不同的CAM设备中实现，包括双端口CAM设备，具有单独位掩码的CAM设备，事件协处理器和数据库协处理器。

13. 发明授权

US06721842B2 Boundary addressable memory 有权
标题翻译：边界可寻址内存
公开(公告)号：US06721842B2
公开(公告)日：2004-04-13
申请号：US10005986
申请日：2001-11-07
申请人： Alex E. Henderson , Walter E. Croft
发明人： Alex E. Henderson , Walter E. Croft
IPC分类号： G06F1200
CPC分类号： H04L49/90 , G11C7/1006 , G11C15/00 , G11C15/04 , H04L29/06 , H04L63/0227 , H04L69/16 , H04L69/161 , H04L69/22 , H04L69/329
摘要： A boundary addressable memory (BAM) array comprises a plurality of BAM word modules, each BAM word module comprises a plurality of BAM cells for performing arithmetic comparisons between input data and an upper bound value and a lower bound value stored in each BAM cell to generate a matching signal indicating whether the input data is not greater than the upper bound value and not less than the lower bound value or whether the input data is not greater than the lower bound value and not less than the upper bound value.
摘要翻译：边界可寻址存储器（BAM）阵列包括多个BAM字模块，每个BAM字模块包括多个BAM单元，用于执行输入数据与存储在每个BAM单元中的上限值和下限值之间的算术比较，以产生指示输入数据是否不大于上限值且不小于下限值的匹配信号，还是输入数据是否不大于下限值且不小于上限值。

14. 发明授权

US4837848A Apparatus for selecting a reference line for image data compression 失效
标题翻译：用于选择用于图像数据压缩的参考线的装置
公开(公告)号：US4837848A
公开(公告)日：1989-06-06
申请号：US32102
申请日：1987-03-27
申请人： Alex E. Henderson , Frederick L. Drain , Lawrence G. Roberts
发明人： Alex E. Henderson , Frederick L. Drain , Lawrence G. Roberts
IPC分类号： H04N1/417
CPC分类号： H04N1/4175
摘要： An apparatus for selecting a reference line for image data compression including a plurality of mutually connected reference selector chips for selecting a reference scan line from vertical mode coding of image data. The reference selector chips select a reference scan line from a plurality of preceding scan lines in exclusive or combination of the image data of each candidate reference scan line with the image data from the input scan line. The candidate reference scan line that has the lowest number of dissimilar bits is selected as the reference scan line. Each candidate reference scan line has associated therewith a register having bit positions arranged from the highest order bit position to a lowest order bit position for storing a binary sum of the number of dissimilar bits. When the sums are compared, the binary value and successive bit positions are compared from the highest order bit position to the lowest order bit position. When the binary value for a compared bit position of a register is greater than the binary value in the corresponding bit position of another register, each reference selector chip generates a losing signal for indicating that the register lost the arbitration. When the lowest order bit position of a register is not greater than the lowest order bit position of any other register and no losing signal was generated for the register, the associated chip generates a winning signal for indicating which candidate reference scan line had the least number of bits dissimilar to the corresponding bits in the input scan line. Each chip further includes a circuit for establishing a priority among the candidate reference scan lines so that two registers both having the smallest binary sum will not create a deadlock.

15. 发明授权

US08547843B2 System, method, and computer program product for controlling output port utilization 有权
标题翻译：用于控制输出端口利用的系统，方法和计算机程序产品
公开(公告)号：US08547843B2
公开(公告)日：2013-10-01
申请号：US11335973
申请日：2006-01-20
申请人： Lawrence G. Roberts , Alex E. Henderson
发明人： Lawrence G. Roberts , Alex E. Henderson
IPC分类号： H04J1/16
CPC分类号： H04L47/10 , H04L47/11 , H04L47/125 , H04L47/22 , H04L47/2416 , H04L47/2441 , H04L47/32
摘要： A system, method and computer program product are provided. In use, a plurality of flows associated with packets destined for an output port is identified. A utilization associated with the output port is further measured. Thus, rates of a plurality of the flows destined for the output port may be individually controlled at an input port thereof, based on the utilization to ensure that the utilization remains less than 99.9% and avoid buffering more than 400 packets with a correspondingly low delay.
摘要翻译：提供了一种系统，方法和计算机程序产品。在使用中，识别与目的地为输出端口的分组相关联的多个流。进一步测量与输出端口相关联的利用率。因此，可以基于利用率单独地控制到输出端口的多个流的速率，以确保利用率保持小于99.9％，并且避免缓冲多于400个具有相应低延迟的分组。

16. 发明申请

US20090034522A1 Transporting fibre channel over ethernet 审中-公开
标题翻译：通过以太网传输光纤通道
公开(公告)号：US20090034522A1
公开(公告)日：2009-02-05
申请号：US11890288
申请日：2007-08-03
申请人： John William Hayes , Linda Elaine Eaton Hayes , Walter E. Croft , Alex E. Henderson
发明人： John William Hayes , Linda Elaine Eaton Hayes , Walter E. Croft , Alex E. Henderson
IPC分类号： H04L12/56
CPC分类号： H04L12/46 , H04L12/4633
摘要： Methods and apparatus for the Transporting of Fibre Channel data over Ethernet are disclosed. In one embodiment of the invention, Fibre Channel data frame and primitive signals are transported over Ethernet instead of using the Fibre Channel FC-1 and FC-0 protocols. This allows less expensive Ethernet equipment and devices to transport and perform services for Fibre Channel connected devices without having a physical Fibre Channel interface. The ability to provide Fibre Channel services and functions without having a physical Fibre Channel interface allows Ethernet equipment to be placed into service as SAN components.
摘要翻译：公开了通过以太网传输光纤通道数据的方法和装置。在本发明的一个实施例中，光纤通道数据帧和原始信号通过以太网传输，而不是使用光纤通道FC-1和FC-0协议。这允许较便宜的以太网设备和设备在没有物理光纤通道接口的情况下传输和执行光纤通道连接设备的服务。在不使用物理光纤通道接口的情况下提供光纤通道服务和功能的能力允许将以太网设备作为SAN组件投入使用。

17. 发明授权

US06446188B1 Caching dynamically allocated objects 失效
标题翻译：缓存动态分配的对象
公开(公告)号：US06446188B1
公开(公告)日：2002-09-03
申请号：US09654189
申请日：2000-09-01
申请人： Alex E. Henderson , Walter E. Croft
发明人： Alex E. Henderson , Walter E. Croft
IPC分类号： G06F1200
CPC分类号： G06F12/1054 , G06F12/023 , G06F12/0292 , G06F12/0875 , G06F2212/45
摘要： A system for mapping a sparsely populated virtual space of variable sized memory objects to a more densely populated physical address space of fixed size memory elements for use by a host processor comprises an object cache for caching frequently accessed memory elements and an object manager for managing the memory objects used by the host processor. The object manager may further comprise an address translation table for translating virtual space addresses for memory objects received from the host processor to physical space addresses for memory elements, and a management table for storing data associated with the memory objects used by the host processor.
摘要翻译：用于将可变大小的存储器对象的稀疏填充的虚拟空间映射到用于由主处理器使用的固定大小的存储器元件的更加密集的物理地址空间的系统包括用于缓存经常访问的存储器元件的对象高速缓存和用于管理主机处理器使用的内存对象。对象管理器还可以包括用于将从主机处理器接收的存储器对象的虚拟空间地址转换为存储器元件的物理空间地址的地址转换表，以及用于存储与主处理器使用的存储器对象相关联的数据的管理表。

18. 发明授权

US06426647B1 Dual rail drive for distributed logic 失效
标题翻译：双轨驱动器用于分布式逻辑
公开(公告)号：US06426647B1
公开(公告)日：2002-07-30
申请号：US09663865
申请日：2000-09-15
申请人： Alex E. Henderson
发明人： Alex E. Henderson
IPC分类号： G06F738
CPC分类号： H03K19/0013
摘要： A logic circuit comprises a dual rail drive circuit having a first rail and a second rail. The logic circuit further comprises a logic block having a first input coupled to receive an input signal from the first rail of the dual rail driver, and a second input coupled to receive an input signal from the second rail of the dual rail driver. In one embodiment, the input signal from the first rail of the dual rail driver can swing to a voltage level sufficient to turn on a p-channel transistor, and the input signal from the second rail of the dual rail driver can swing to a voltage level sufficient to turn on an n-channel transistor. For example, for a 0.18 micron process the input signal from the first rail may have a voltage swing from VDD to VDD-400 MV, and the input signal from the second rail may a voltage swing from GROUND to 400 MV.
摘要翻译：逻辑电路包括具有第一导轨和第二导轨的双轨驱动电路。逻辑电路还包括逻辑块，其具有被耦合以接收来自双轨驱动器的第一轨的输入信号的第一输入和耦合以从双轨驱动器的第二轨接收输入信号的第二输入。在一个实施例中，来自双轨驱动器的第一导轨的输入信号可以摆动到足以导通p沟道晶体管的电压电平，并且来自双轨驱动器的第二导轨的输入信号可以摆动到电压电平足以导通n沟道晶体管。例如，对于0.18微米工艺，来自第一导轨的输入信号可以具有从VDD到VDD-400MV的电压摆幅，并且来自第二导轨的输入信号可以从地电压摆幅到400MV。

19. 发明申请

US20130208732A1 Transporting Fibre Channel over Ethernet 审中-公开
标题翻译：通过以太网传输光纤通道
公开(公告)号：US20130208732A1
公开(公告)日：2013-08-15
申请号：US13385390
申请日：2012-02-15
申请人： Alex E. Henderson , John William Hayes , Linda Elaine Eaton Hayes , Walter E. Croft
发明人： Alex E. Henderson , John William Hayes , Linda Elaine Eaton Hayes , Walter E. Croft
IPC分类号： H04L12/56
CPC分类号： H04L12/4633 , H04L12/4625 , H04Q2213/1301 , H04Q2213/13389
摘要： Methods and apparatus for the Transporting of Fibre Channel data over Ethernet are disclosed. In one embodiment of the invention, Fibre Channel data frame and primitive signals are transported over Ethernet instead of using the Fibre Channel FC-1 and FC-0 protocols. This allows less expensive Ethernet equipment and devices to transport and perform services for Fibre Channel connected devices without having a physical Fibre Channel interface. The ability to provide Fibre Channel services and functions without having a physical Fibre Channel interface allows existing Ethernet equipment to be placed into service as SAN components without modification.
摘要翻译：公开了通过以太网传输光纤通道数据的方法和装置。在本发明的一个实施例中，光纤通道数据帧和原始信号通过以太网传输，而不是使用光纤通道FC-1和FC-0协议。这允许较便宜的以太网设备和设备在没有物理光纤通道接口的情况下传输和执行光纤通道连接设备的服务。在没有物理光纤通道接口的情况下提供光纤通道服务和功能的能力允许现有以太网设备作为SAN组件投入使用而无需修改。

20. 发明授权

US07333484B2 Services processor having a packet editing unit 有权
标题翻译：服务处理器具有分组编辑单元
公开(公告)号：US07333484B2
公开(公告)日：2008-02-19
申请号：US10359042
申请日：2003-02-04
申请人： Alex E. Henderson , Walter E. Croft
发明人： Alex E. Henderson , Walter E. Croft
IPC分类号： H04L12/56 , H04L12/54
CPC分类号： H04L67/2804 , H04L29/06 , H04L47/564 , H04L47/6215 , H04L47/623 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L63/0227 , H04L67/2842 , H04L69/16 , H04L69/161 , H04L69/22 , H04L69/329
摘要： A services processor includes an editing unit, which performs various functions for editing data packets, such as packet creation, packet encapsulation, and packet replication.
摘要翻译：服务处理器包括编辑单元，其执行用于编辑数据分组的各种功能，诸如分组创建，分组封装和分组复制。

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