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11. 发明申请

US20090064078A1 Method of designing a semiconductor integrated circuit having a dummy area and the semiconductor integrated circuit thereof 有权
标题翻译：具有虚拟区域的半导体集成电路及其半导体集成电路的设计方法
公开(公告)号：US20090064078A1
公开(公告)日：2009-03-05
申请号：US12230309
申请日：2008-08-27
申请人： Yoshitaka Kimura
发明人： Yoshitaka Kimura
IPC分类号： G06F17/50 , H01L23/48
CPC分类号： H01L23/544 , G06F17/5077 , H01L2223/54406 , H01L2223/54433 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： An exemplary semiconductor integrated circuit is formed on a surface of a semiconductor chip includes a circuit region and a dummy region on the surface of the semiconductor chip. The circuit region includes a plurality of circuit patterns, which form circuit elements of the semiconductor integrated circuit, in a plurality of pattern layers. The dummy region includes a plurality of character dummies, which do not contribute to an operation of the semiconductor integrated circuit. The character dummies have a fixed shape and dimension, and arranged in a character pattern layer selected from the plurality of pattern layers with a fixed pitch. The dummy region further includes an identification sign formed by connecting selected ones of the character dummies chosen from the plurality of the character dummies.
摘要翻译：在半导体芯片的表面上形成示例性半导体集成电路，其包括在半导体芯片的表面上的电路区域和虚设区域。电路区域包括在多个图案层中形成半导体集成电路的电路元件的多个电路图案。虚拟区域包括不对半导体集成电路的操作有贡献的多个字符虚拟。字符虚拟具有固定的形状和尺寸，并且以固定间距排列在从多个图案层中选择的字符图案层中。虚拟区域还包括通过连接从多个角色虚拟人物中选择的所选角色虚拟人物形成的识别符号。

12. 发明授权

US07432115B2 Test circuit, semiconductor product wafer having the test circuit, and method of monitoring manufacturing process using the test circuit 有权
标题翻译：测试电路，具有测试电路的半导体产品晶片，以及使用测试电路监测制造工艺的方法
公开(公告)号：US07432115B2
公开(公告)日：2008-10-07
申请号：US11808861
申请日：2007-06-13
申请人： Eita Kinoshita
发明人： Eita Kinoshita
IPC分类号： H01L21/00
CPC分类号： H01L22/34 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested; a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.
摘要翻译：提供了使用该测试电路监测半导体集成电路的制造工艺的测试电路和方法。测试电路包括要测试的元件; 选择电路，用于一次顺序地选择所述元件中的至少一个。用于测试元件的测试电路和焊盘被放置在半导体晶片上的划线内。

13. 发明授权

US07301797B2 Method of operating semiconductor integrated circuit including SRAM block and semiconductor integrated circuit including SRAM block 有权
标题翻译：包括SRAM块和包括SRAM块的半导体集成电路的半导体集成电路的操作方法
公开(公告)号：US07301797B2
公开(公告)日：2007-11-27
申请号：US11086751
申请日：2005-03-23
申请人： Yoshitaka Kimura
发明人： Yoshitaka Kimura
IPC分类号： G11C11/00
CPC分类号： G11C11/419
摘要： A method of operating a semiconductor integrated circuit including a SRAM block, in which non-volatile data is stored in the SRAM block, is disclosed. In an exemplary embodiment, the non-volatile data is stored by flowing a drain current in one of a pair of pull-down transistors constituting the SRAM cell while supplying a fixed potential to the sources of the pull-down transistors. A semiconductor integrated circuit including a SRAM block and a control circuit that controls the SRAM block to store non-volatile data is also disclosed.
摘要翻译：公开了一种包括其中非易失性数据被存储在SRAM块中的SRAM块的半导体集成电路的操作方法。在示例性实施例中，通过在构成SRAM单元的一对下拉晶体管中的一个中流过漏极电流，同时向下拉晶体管的源提供固定电位来存储非易失性数据。还公开了一种包括SRAM块和控制SRAM块以存储非易失性数据的控制电路的半导体集成电路。

14. 发明申请

US20070253276A1 Method of preventing dielectric breakdown of semiconductor device and semiconductor device preventing dielectric breakdown 有权
标题翻译：防止绝缘击穿的半导体器件和半导体器件的绝缘击穿的方法
公开(公告)号：US20070253276A1
公开(公告)日：2007-11-01
申请号：US11790035
申请日：2007-04-23
申请人： Tsuneo Ochi
发明人： Tsuneo Ochi
IPC分类号： G11C8/00
CPC分类号： G02F1/13452 , G02F1/136204 , H01L23/585 , H01L24/06 , H01L2224/0401 , H01L2924/01004 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/14 , H01L2924/19043 , H01L2924/30105
摘要： A semiconductor device that prevents a build-up of electrostatic charge in a dummy pad is provided. The semiconductor device may contain an internal circuit formed on a semiconductor substrate and the dummy pad which is not electrically connected to the internal circuit. The semiconductor device may further include a seal ring that surrounds the internal circuit and the dummy pad, where the seal ring is electrically connected to the semiconductor substrate and includes a pattern in a first metal layer, a contact between the pattern in the first metal layer and the semiconductor substrate, patterns in upper metal layers stacked above the pattern in the first metal layer, and multiple electrical contacts between the patterns in the first metal layer and the upper metal layers, in which the dummy pad is electrically connected to the seal ring.
摘要翻译：提供一种防止在虚拟垫中积聚静电电荷的半导体装置。半导体器件可以包含形成在半导体衬底上的内部电路和不与内部电路电连接的虚拟焊盘。半导体器件还可以包括密封环，该密封环围绕内部电路和虚拟焊盘，其中密封环电连接到半导体衬底并且包括第一金属层中的图案，第一金属层中的图案之间的接触并且半导体衬底，堆叠在第一金属层中的图案之上的上金属层中的图案以及第一金属层中的图案与上金属层之间的多个电接触，其中虚拟焊盘与密封环电连接。

15. 发明授权

US07218162B2 Semiconductor integrated circuit having output circuit 有权
标题翻译：具有输出电路的半导体集成电路
公开(公告)号：US07218162B2
公开(公告)日：2007-05-15
申请号：US11340697
申请日：2006-01-27
申请人： Ryuji Ariyoshi
发明人： Ryuji Ariyoshi
IPC分类号： H03H11/26 , H03K3/356
CPC分类号： H03K17/302 , H03K19/0013 , H03K19/018521
摘要： A semiconductor integrated circuit that has an output circuit in which an output-stage operating voltage lower than a power supply voltage is applied to an output stage is provided. Even when the power supply voltage is lowered, a sufficient output signal amplitude can be obtained. An increase in circuit scale can be prevented and the power consumption can be reduced. An output-stage operating voltage supply source, including an N-channel MOS transistor having a first threshold voltage, applies an operating voltage lower than a power supply voltage to the output stage of the output circuit. A drive-circuit operating voltage supply source, including an N-channel MOS transistor having a second threshold voltage lower than the first threshold voltage, applies a drive-circuit operating voltage higher than the output-stage operating voltage to a drive circuit.
摘要翻译：提供一种具有输出电路的半导体集成电路，其中将低于电源电压的输出级工作电压施加到输出级。即使当电源电压降低时，也可以获得足够的输出信号幅度。可以防止电路规模的增加并且能够降低功耗。包括具有第一阈值电压的N沟道MOS晶体管的输出级工作电压源，向输出电路的输出级施加低于电源电压的工作电压。包括具有低于第一阈值电压的第二阈值电压的N沟道MOS晶体管的驱动电路工作电压源施加比驱动电路高出输出级工作电压的驱动电路工作电压。

16. 发明申请

US20060102928A1 Method of manufacturing semiconductor device and the semiconductor device manufactured by the method 有权
标题翻译：通过该方法制造半导体器件和半导体器件的方法
公开(公告)号：US20060102928A1
公开(公告)日：2006-05-18
申请号：US11266371
申请日：2005-11-04
申请人： Ryo Nakamura
发明人： Ryo Nakamura
IPC分类号： H01L29/74
CPC分类号： H01L29/7833 , H01L21/823418 , H01L21/823456 , H01L21/823462 , H01L21/823814 , H01L21/82385 , H01L21/823857 , H01L29/6659
摘要： The method of manufacturing the semiconductor device that includes a high voltage MOS transistor with high operating voltage under both high and low gate voltages with low-cost is disclosed. When manufacturing the high voltage MOS transistor, a portion of a gate insulation film is removed to form an opening that exposes an outside area of the active area, which is outside of the central area where a gate electrode will be formed. A shallow grade layer is formed by implanting impurities into an opening with an energy that does not permit penetration of impurity ions through the gate insulation film.
摘要翻译：公开了一种制造半导体器件的方法，该半导体器件包括具有低工作电压的高电压MOS晶体管，具有低栅极电压和低栅极电压。当制造高压MOS晶体管时，去除栅极绝缘膜的一部分以形成暴露出将形成栅电极的中心区域外部的有源区的外部区域的开口。通过以不能使杂质离子穿过栅极绝缘膜的能量将杂质注入开口形成浅层。

17. 发明授权

US07034626B2 Oscillator with closed series of four inductors and four capacitors with connecting nodes 有权
标题翻译：振荡器具有闭合系列的四个电感器和四个具有连接节点的电容器
公开(公告)号：US07034626B2
公开(公告)日：2006-04-25
申请号：US10250426
申请日：2002-01-08
申请人： Koichi Akeyama , Peter Vancorenland
发明人： Koichi Akeyama , Peter Vancorenland
IPC分类号： H03B1/00
CPC分类号： H03B27/00 , H03B5/1215 , H03B5/1228 , H03B5/1253
摘要： An object of the present invention is to provide an oscillator contributing to a reduction of power dissipation. An oscillator 10 comprises four inductors 11—1, 11—3, 11—2, and 11—4 connected in series to constitute a closed circuit, and four capacitors 12—1, 12—3, 12—2, and 12—4 one ends of which are connected to nodes that are connecting points of the inductors, and another ends of which are held at a power supply VDD. The oscillator 10 is formed on a semiconductor substrate.
摘要翻译：本发明的目的是提供一种有助于降低功耗的振荡器。振荡器10包括四个电感器11，11，...，11，11，...，11，...，串联连接以构成闭合电路，以及四个电容器12 1 - 12,12 - 3 - 12 - 2和12 - - 其一端连接到作为电感器的连接点的节点，并且其另一端保持在电源V DD上。振荡器10形成在半导体衬底上。

18. 发明授权

US07023906B2 Receiver and receiving method in spread spectrum communication system 有权
标题翻译：扩频通信系统中的接收和接收方法
公开(公告)号：US07023906B2
公开(公告)日：2006-04-04
申请号：US09793492
申请日：2001-02-27
申请人： Takaharu Sato , Takashi Ueda
发明人： Takaharu Sato , Takashi Ueda
IPC分类号： H04B1/69
CPC分类号： H04B1/70757 , H04B1/7093
摘要： An over-sampling circuit is provided at a front stage of a digital matched filter, and a received signal is over-sampled with it. Synchronous acquisition of the received spread spectrum signal is implemented by adding the data obtained by the over-sampling, inputting it into the digital matched filter, and then performing a correlation thereon.
摘要翻译：在数字匹配滤波器的前级提供过采样电路，并且接收信号被过采样。通过将通过过采样获得的数据相加，将其输入到数字匹配滤波器中，然后在其上执行相关来实现接收的扩频信号的同步采集。

19. 发明申请

US20050213371A1 Method of operating semiconductor integrated circuit including SRAM block and semiconductor integrated circuit including SRAM block 有权
标题翻译：包括SRAM块和包括SRAM块的半导体集成电路的半导体集成电路的操作方法
公开(公告)号：US20050213371A1
公开(公告)日：2005-09-29
申请号：US11086751
申请日：2005-03-23
申请人： Yoshitaka Kimura
发明人： Yoshitaka Kimura
IPC分类号： G11C11/41 , G11C11/419
CPC分类号： G11C11/419
摘要： A method of operating a semiconductor integrated circuit including a SRAM block, in which non-volatile data is stored in the SRAM block, is disclosed. In an exemplary embodiment, the non-volatile data is stored by flowing a drain current in one of a pair of pull-down transistors constituting the SRAM cell while supplying a fixed potential to the sources of the pull-down transistors. A semiconductor integrated circuit including a SRAM block and a control circuit that controls the SRAM block to store non-volatile data is also disclosed.
摘要翻译：公开了一种包括其中非易失性数据被存储在SRAM块中的SRAM块的半导体集成电路的操作方法。在示例性实施例中，通过在构成SRAM单元的一对下拉晶体管中的一个中流过漏极电流，同时向下拉晶体管的源提供固定电位来存储非易失性数据。还公开了一种包括SRAM块和控制SRAM块以存储非易失性数据的控制电路的半导体集成电路。

20. 发明申请

US20050013179A1 Content addressable memory capable of changing priority in priority encoder 有权
标题翻译：内容可寻址存储器能够改变优先级编码器的优先级
公开(公告)号：US20050013179A1
公开(公告)日：2005-01-20
申请号：US10854282
申请日：2004-05-27
申请人： Naoki Kanazawa
发明人： Naoki Kanazawa
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A content addressable memory includes a plurality of word memories which respectively have assigned addresses, and each outputs a match/mismatch signal representing storage or no storage of a data item matching search data in a search mode, a priority encoder which output addresses of word memories which output the match signals in the search mode in predetermined fixed priority order, a first prior word-memory setting section for setting a first prior word memory, and a priority changing part which masks the match signals output from upper-positional word memories of the word memories, which correspond to word memories having upper positions compared with the first prior word memory in the fixed priority order in the priority encoder, and transmits signals representing that the word memories having the upper positions output no match signals to the priority encoder.
摘要翻译：内容可寻址存储器包括分别具有分配地址的多个字存储器，并且各自输出表示在搜索模式中与搜索数据匹配的数据项的存储或不存储的匹配/失配信号，输出字存储器的地址的优先编码器其以预定的固定优先级顺序输出搜索模式中的匹配信号，用于设置第一先前字存储器的第一先前字存储器设置部分和屏蔽从上位字词存储器输出的匹配信号的优先级改变部分对应于优先编码器中固定优先级顺序与第一先前字存储器相比较的具有上位置的字存储器的字存储器，并且将表示具有上位置的字存储器的信号发送给优先编码器。

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