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171. 发明申请

US20060134866A1 NON-VOLATILE MEMORY AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20060134866A1
公开(公告)日：2006-06-22
申请号：US11018507
申请日：2004-12-20
申请人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
发明人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42348 , H01L29/66833 , H01L29/7923
摘要： A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.
摘要翻译：提供非易失性存储器。存储器包括衬底，电介质层，导电层，隔离层，掩埋位线，隧道电介质层，电荷俘获层，势垒介电层和字线。其中介电层设置在基板上。导电层设置在电介质层上。隔离层设置在基板上并且邻近电介质层和导电层。掩埋位线设置在衬底中并在隔离层下方。隧道电介质层设置在导电层和隔离层的基板和侧壁上。电荷捕获层设置在隧道介电层上，势垒介电层设置在电荷俘获层上。字线设置在基板上，与埋入位线交叉。

172. 发明授权

US07030459B2 Three-dimensional memory structure and manufacturing method thereof 有权
标题翻译：三维记忆结构及其制造方法
公开(公告)号：US07030459B2
公开(公告)日：2006-04-18
申请号：US10906779
申请日：2005-03-07
申请人： Erh-Kun Lai , Ming-Chung Liang
发明人： Erh-Kun Lai , Ming-Chung Liang
IPC分类号： H01L29/00
CPC分类号： H01L27/1021 , H01L21/8221 , H01L23/5252 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional memory structure and manufacturing method thereof is provided. A first stack layer is formed over a substrate. The first stack layer includes, from the substrate upwards, an n-type polysilicon layer, a conductive layer, an anti-fuse and another n-type polysilicon layer. The first stack layer is patterned to form a first stack circuit. Thereafter, a second stack layer is formed over the first stack circuit. The second stack layer includes, from the first stack circuit upwards, a p-type polysilicon layer, a conductive layer, an anti-fuse and another p-type polysilicon. The second stack layer is patterned to form a second stack circuit that crosses over the first stack circuit perpendicularly. The aforementioned steps are repeated to form more stack circuits above the substrate and hence produce a three-dimensional structure.
摘要翻译：提供三维记忆结构及其制造方法。第一堆叠层形成在衬底上。第一堆叠层从衬底向上包括n型多晶硅层，导电层，反熔丝和另一n型多晶硅层。图案化第一堆叠层以形成第一堆叠电路。此后，在第一堆叠电路上形成第二堆叠层。第二堆叠层从第一堆叠电路向上包括p型多晶硅层，导电层，反熔丝和另一p型多晶硅。图案化第二堆叠层以形成垂直于第一堆叠电路的第二堆叠电路。重复上述步骤以在衬底上形成更多的堆叠电路，并因此产生三维结构。

173. 发明申请

US20050006719A1 [THREE-DIMENSIONAL MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF] 审中-公开
标题翻译： [三维存储器结构及其制造方法]
公开(公告)号：US20050006719A1
公开(公告)日：2005-01-13
申请号：US10604042
申请日：2003-06-24
申请人： Erh-Kun Lai , Ming-Chung Liang
发明人： Erh-Kun Lai , Ming-Chung Liang
IPC分类号： H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/525 , H01L27/06 , H01L29/00
CPC分类号： H01L27/1021 , H01L21/8221 , H01L23/5252 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional memory structure and manufacturing method thereof is provided. A first stack layer is formed over a substrate. The first stack layer includes, from the substrate upwards, an n-type polysilicon layer, a conductive layer, an anti-fuse and another n-type polysilicon layer. The first stack layer is patterned to form a first stack circuit. Thereafter, a second stack layer is formed over the first stack circuit. The second stack layer includes, from the first stack circuit upwards, a p-type polysilicon layer, a conductive layer, an anti-fuse and another p-type polysilicon. The second stack layer is patterned to form a second stack circuit that crosses over the first stack circuit perpendicularly. The aforementioned steps are repeated to form more stack circuits above the substrate and hence produce a three-dimensional structure.
摘要翻译：提供三维记忆结构及其制造方法。第一堆叠层形成在衬底上。第一堆叠层从衬底向上包括n型多晶硅层，导电层，反熔丝和另一n型多晶硅层。图案化第一堆叠层以形成第一堆叠电路。此后，在第一堆叠电路上形成第二堆叠层。第二堆叠层从第一堆叠电路向上包括p型多晶硅层，导电层，反熔丝和另一p型多晶硅。图案化第二堆叠层以形成垂直于第一堆叠电路的第二堆叠电路。重复上述步骤以在衬底上形成更多的堆叠电路，并因此产生三维结构。

174. 发明授权

US06790720B1 Method for fabricating a MOSFET and reducing line width of gate structure 有权
标题翻译：制造MOSFET并减少栅极结构的线宽的方法
公开(公告)号：US06790720B1
公开(公告)日：2004-09-14
申请号：US10605360
申请日：2003-09-25
申请人： Erh-Kun Lai
发明人： Erh-Kun Lai
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/28052 , H01L29/665 , H01L29/7833
摘要： A method for fabricating a MOSFET is provided. The method comprises: providing a substrate, the substrate having a gate structure; forming a drain region and a source region in the substrate, the drain region and the source region being on two sides of the gate structure respectively; forming a metal suicide layer on the surface of the gate structure, the drain region, and the source region; forming a patterned block on the metal silicide layer above the gate structure, and forming a first dielectric layer above the substrate except the gate strcutre, the patterned block being formed above the center of the gate structure and the metal silicide layer above the gate structure beside two sides of the patterned block being exposed; removing a portion of the metal silicide layer and a portion of the gate structure by using the patterned block as a mask; and forming a drain extension region and a source extension region in the substrate, beside two sides of the remaining gate structure.
摘要翻译：提供了一种用于制造MOSFET的方法。该方法包括：提供衬底，所述衬底具有栅极结构; 在所述衬底中形成漏极区和源极区，所述漏极区和所述源极区分别位于所述栅极结构的两侧; 在栅极结构，漏极区域和源极区域的表面上形成金属硅化物层; 在所述栅极结构上方的所述金属硅化物层上形成图案化块，以及在所述栅极结构之外的所述衬底之上形成第一电介质层，所述图案化块形成在所述栅极结构的中心之上，并且所述栅极结构上方的所述金属硅化物层在图案化块的两侧被暴露; 通过使用图案化块作为掩模去除金属硅化物层的一部分和栅极结构的一部分; 以及在所述衬底中在所述剩余栅极结构的两侧旁边形成漏极延伸区域和源极延伸区域。

175. 发明授权

US06599801B1 Method of fabricating NROM memory cell 有权
标题翻译：制造NROM记忆体的方法
公开(公告)号：US06599801B1
公开(公告)日：2003-07-29
申请号：US10178524
申请日：2002-06-25
申请人： Kent Kuohua Chang , Erh-Kun Lai
发明人： Kent Kuohua Chang , Erh-Kun Lai
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573
摘要： A method of fabricating NROM memory cell, wherein the NROM device comprises a memory array and a peripheral portion. The fabricating method comprising the steps of: providing a substrate which a oxide layer is formed thereon; forming a peripheral polysilicon layer on the oxide layer; defining a patterned peripheral polysilicon; forming an ONO layer over the substrate in the memory array and the peripheral portion; forming an array polysilicon layer on the ONO layer; and defining a patterned array polysilicon. The method of fabricating NROM memory cell according to the invention can solve the problems of top oxide loss, touch between nitride and polysilicon, and BD over-diffusion.
摘要翻译：一种制造NROM存储单元的方法，其中NROM器件包括存储器阵列和外围部分。该制造方法包括以下步骤：提供在其上形成氧化物层的衬底; 在所述氧化物层上形成外围多晶硅层; 限定图案化的外围多晶硅; 在存储器阵列和周边部分中的衬底上形成ONO层; 在ONO层上形成阵列多晶硅层; 并且限定图案化阵列多晶硅。根据本发明的制造NROM存储单元的方法可以解决顶部氧化物损失，氮化物和多晶硅之间的接触以及BD过度扩散的问题。

176. 发明授权

US06440798B1 Method of forming a mixed-signal circuit embedded NROM memory and MROM memory 有权
标题翻译：形成嵌入式NROM存储器和MROM存储器的混合信号电路的方法
公开(公告)号：US06440798B1
公开(公告)日：2002-08-27
申请号：US09682148
申请日：2001-07-26
申请人： Erh-Kun Lai , Chien-Hung Liu , Shou-Wei Huang , Shyi-Shuh Pan , Ying-Tso Chen
发明人： Erh-Kun Lai , Chien-Hung Liu , Shou-Wei Huang , Shyi-Shuh Pan , Ying-Tso Chen
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： The present invention gives a method for creating a NROM memory from a semiconductor substrate. Numerous process steps are included to achieve this including forming shallow trench isolation areas, many ion implantation processes, ROM code implantation processes, photolithography and creation of layers and removal of layers. At the end of the process a mixed-signal circuit embedded NROM and NROM memory are created.
摘要翻译：本发明提供了一种从半导体衬底生成NROM存储器的方法。包括许多工艺步骤以实现这一点，包括形成浅沟槽隔离区域，许多离子注入工艺，ROM代码注入工艺，光刻以及层的创建和层的去除。在该过程结束时，创建了嵌入NROM和NROM存储器的混合信号电路。

177. 发明授权

US08933536B2 Polysilicon pillar bipolar transistor with self-aligned memory element 有权
标题翻译：具有自对准存储元件的多晶硅柱双极晶体管
公开(公告)号：US08933536B2
公开(公告)日：2015-01-13
申请号：US12357912
申请日：2009-01-22
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Chung H. Lam , Bipin Rajendran
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Chung H. Lam , Bipin Rajendran
IPC分类号： H01L27/082 , H01L27/102 , H01L27/24 , H01L45/00
CPC分类号： H01L27/1026 , H01L27/2445 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1625 , H01L45/1683
摘要： Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter.
摘要翻译：本文描述了具有与双极结晶体管存取装置的发射极自对准的存储元件的存储单元以及用于制造这种装置的方法。如本文所述的存储器件包括多个存储器单元。多个存储单元中的存储单元包括双极结型晶体管，其包括由掺杂多晶硅柱构成的发射极。存储单元包括在发射器上的绝缘元件，并且具有延伸穿过绝缘层的开口，开口以发射器为中心。存储单元还包括在开口内的存储元件并电耦合到发射器。

178. 发明申请

US20140042629A1 SEMICONDUCTING MULTI-LAYER STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体多层结构及其制造方法
公开(公告)号：US20140042629A1
公开(公告)日：2014-02-13
申请号：US13584366
申请日：2012-08-13
申请人： Erh-Kun Lai , Yen-Hao Shih
发明人： Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L23/485 , H01L21/28
CPC分类号： H01L27/11582 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A semiconducting multi-layer structure comprising a plurality of first conductive layers, a plurality of first insulating layers and a second conductive layer is disclosed. The first conductive layers are separately disposed. Each of the first conductive layers has an upper surface, a bottom surface opposite to the upper surface and a lateral surface. The first insulating layers surround the peripherals of the first conductive layers. Each of the first insulating layers covers at least a part of the upper surface of each of the first conductive layers, at least a part of the bottom surface of each of the first conductive layers and the two lateral surface of each of the first conductive layers. The second conductive layer covers the first conductive layers and the first insulating layers.
摘要翻译：公开了一种包括多个第一导电层，多个第一绝缘层和第二导电层的半导体多层结构。第一导电层分开设置。每个第一导电层具有上表面，与上表面相对的底表面和侧表面。第一绝缘层围绕第一导电层的外围设备。每个第一绝缘层覆盖每个第一导电层的上表面的至少一部分，每个第一导电层的每个的底表面的至少一部分和每个第一导电层的两个侧表面。第二导电层覆盖第一导电层和第一绝缘层。

179. 发明授权

US08481388B2 Non-volatile memory device having a nitride-oxide dielectric layer 有权
标题翻译：具有氮化物 - 氧化物电介质层的非易失性存储器件
公开(公告)号：US08481388B2
公开(公告)日：2013-07-09
申请号：US12818057
申请日：2010-06-17
申请人： Chao-I Wu , Tzu-Hsuan Hsu , Hang-Ting Lue , Erh-Kun Lai
发明人： Chao-I Wu , Tzu-Hsuan Hsu , Hang-Ting Lue , Erh-Kun Lai
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L29/513
摘要： A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.
摘要翻译：非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

180. 发明授权

US08310864B2 Self-aligned bit line under word line memory array 有权
标题翻译：字线内存阵列下的自对准位线
公开(公告)号：US08310864B2
公开(公告)日：2012-11-13
申请号：US12815680
申请日：2010-06-15
申请人： Hsiang-Lan Lung , Chung H Lam , Erh-Kun Lai , Matthew J. Breitwisch
发明人： Hsiang-Lan Lung , Chung H Lam , Erh-Kun Lai , Matthew J. Breitwisch
IPC分类号： G11C11/00
CPC分类号： H01L27/2454 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148
摘要： A memory device is described that comprises a plurality of bit lines and an array of vertical transistors arranged on the plurality of bit lines. A plurality of word lines is formed along rows of vertical transistors in the array which comprise thin film sidewalls of word line material and arranged so that the thin film sidewalls merge in the row direction, and do not merge in the column direction, to form word lines. The word lines provide “surrounding gate” structures for embodiments in which the vertical transistors are field effect transistors. Memory elements are formed in electrical communication with the vertical transistors. A fully self-aligned process is provided in which the word lines and memory elements are aligned with the vertical transistors without additional patterning steps.
摘要翻译：描述了包括多个位线和布置在多个位线上的垂直晶体管阵列的存储器件。多个字线沿阵列中的垂直晶体管行形成，其中包括字线材料的薄膜侧壁，并且布置成使得薄膜侧壁在行方向上合并，并且不在列方向上合并，以形成字线条。对于其中垂直晶体管是场效应晶体管的实施例，字线提供周围的栅极结构。存储元件形成为与垂直晶体管电连通。提供了完全自对准的工艺，其中字线和存储元件与垂直晶体管对准，而没有额外的图案化步骤。

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