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171. 发明申请

US20090049248A1 Reducing Wiring Congestion in a Cache Subsystem Utilizing Sectored Caches with Discontiguous Addressing 失效
标题翻译：减少使用不连续寻址的扇区高速缓存子系统中的接线拥塞
公开(公告)号：US20090049248A1
公开(公告)日：2009-02-19
申请号：US11839663
申请日：2007-08-16
申请人： Leo James Clark , James Stephen Fields, JR. , Guy Lynn Guthrie , William John Starke , Derek Edward Williams , Phillip G. Williams
发明人： Leo James Clark , James Stephen Fields, JR. , Guy Lynn Guthrie , William John Starke , Derek Edward Williams , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0851 , G06F12/0864
摘要： A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.
摘要翻译：一种方法和计算机系统，用于通过重新配置扇区到片分配和较低的高速缓存寻址方案来减少具有扇区和分片的低级高速缓存的高速缓存子系统中的布线拥塞，所需的房地产和访问延迟。通过这种分配，具有不连续地址的扇区被放置在相同的片内，并且基于对高速缓存片内的可寻址扇区的这种重新分配，可以在两级低级高速缓存之间进行简化布线方案。此外，低速缓存有效地址标签被重新配置，使得先前分配用于识别扇区和片的地址字段相对于地址标签内的彼此的位置被切换。地址位的这种重新分配使得能够基于指示的扇区进行直接片寻址。

172. 发明授权

US07454577B2 Data processing system and method for efficient communication utilizing an Tn and Ten coherency states 有权
公开(公告)号：US07454577B2
公开(公告)日：2008-11-18
申请号：US11055476
申请日：2005-02-10
申请人： James Stephen Fields, Jr. , Benjiman Lee Goodman , Guy Lynn Guthrie , William John Starke , Derek Edward Williams
发明人： James Stephen Fields, Jr. , Benjiman Lee Goodman , Guy Lynn Guthrie , William John Starke , Derek Edward Williams
IPC分类号： G06F13/00
CPC分类号： G06F12/0817 , G06F12/0831 , G06F12/084
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

173. 发明授权

US07305523B2 Cache memory direct intervention 失效
标题翻译：缓存内存直接干预
公开(公告)号：US07305523B2
公开(公告)日：2007-12-04
申请号：US11056673
申请日：2005-02-12
申请人： Guy Lynn Guthrie , William John Starke , Derek Edward Williams
发明人： Guy Lynn Guthrie , William John Starke , Derek Edward Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0831 , G06F12/127
摘要： A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss.
摘要翻译：一种用于实现跨层级高速缓冲存储器的干预的方法，系统和设备。在优选实施例中，响应于第一高速缓冲存储器中的高速缓存未命中，直接干预请求从第一高速缓存存储器发送到第二高速缓存存储器，请求满足高速缓存未命中的直接干预。

174. 发明授权

US07284102B2 System and method of re-ordering store operations within a processor 失效
标题翻译：在处理器内重新排序存储操作的系统和方法
公开(公告)号：US07284102B2
公开(公告)日：2007-10-16
申请号：US11054450
申请日：2005-02-09
申请人： Guy Lynn Guthrie , Hugh Shen , William John Starke , Derek Edward Williams
发明人： Guy Lynn Guthrie , Hugh Shen , William John Starke , Derek Edward Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/3824 , G06F12/0817
摘要： A system and method for re-ordering store operations from a processor core to a store queue. When a store queue receives a new processor-issued store operation from the processor core, a store queue controller allocates a new entry in the store queue. In response to allocating the new entry in the store queue, the store queue controller determines whether or not the new entry is dependent on at least one other valid entry in the store queue. In response to determining the new entry is dependent on at least one other valid entry in the store queue, the store queue controller inhibits requesting of the new entry to the RC dispatch logic until each valid entry on which the new entry is dependent has been successfully dispatched to an RC machine by the RC dispatch logic.
摘要翻译：一种用于重新排序从处理器核到存储队列的存储操作的系统和方法。当存储队列从处理器核心接收到新的处理器发出的存储操作时，存储队列控制器在存储队列中分配新的条目。响应于在商店队列中分配新条目，商店队列控制器确定新条目是否依赖于商店队列中的至少一个其他有效条目。响应于确定新条目取决于存储队列中的至少一个其他有效条目，存储队列控制器禁止向RC调度逻辑请求新条目，直到新条目依赖于其上的每个有效条目已经成功通过RC调度逻辑调度到RC机器。

175. 发明授权

US08140765B2 Information handling system with immediate scheduling of load operations in a dual-bank cache with single dispatch into write/read data flow 有权
标题翻译：信息处理系统，可以在双行缓存中立即调度负载操作，并单次调度到写入/读取数据流
公开(公告)号：US08140765B2
公开(公告)日：2012-03-20
申请号：US12424228
申请日：2009-04-15
申请人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F13/28
CPC分类号： G06F12/0846 , G06F12/0897
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。缓存系统向数据流提供单个调度点到L2缓存存储器的双缓存组。

176. 发明授权

US08140759B2 Specifying an access hint for prefetching partial cache block data in a cache hierarchy 失效
标题翻译：指定用于在缓存层次结构中预取部分高速缓存块数据的访问提示
公开(公告)号：US08140759B2
公开(公告)日：2012-03-20
申请号：US12424716
申请日：2009-04-16
申请人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
发明人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0817 , G06F2212/6028
摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.
摘要翻译：用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。

177. 发明授权

US08001330B2 L2 cache controller with slice directory and unified cache structure 失效
标题翻译： L2缓存控制器具有片目录和统一缓存结构
公开(公告)号：US08001330B2
公开(公告)日：2011-08-16
申请号：US12325266
申请日：2008-12-01
申请人： Leo James Clark , James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke
发明人： Leo James Clark , James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F13/00
CPC分类号： G06F12/0851 , G06F12/0811
摘要： A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.
摘要翻译：缓存存储器将具有单个访问/命令端口的高速缓存阵列逻辑地分区成至少两个切片，并且使用第一目录来访问第一阵列片，同时使用第二目录来访问第二阵列片，但是从高速缓存目录使用控制单个访问/命令端口的单个缓存仲裁器进行管理。在一个实施例中，每个高速缓存目录具有其自己的目录仲裁器来处理冲突的内部请求，并且目录仲裁器与高速缓存仲裁器通信。高速缓存阵列布置有高速缓存扇区的行和列，其中高速缓存行分布在不同行和列中的扇区之间，其中一部分给定高速缓存行位于具有第一延迟的第一列中，并且给定的另一部分高速缓存线位于具有大于第一等待时间的第二等待时间的第二列中。

178. 发明申请

US20100268895A1 INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS 审中-公开
标题翻译：信息处理系统，立即加载运行
公开(公告)号：US20100268895A1
公开(公告)日：2010-10-21
申请号：US12424284
申请日：2009-04-15
申请人： Sanjeev Ghai , Guy Lynn Guthrie , Stephen Powell , William John Starke
发明人： Sanjeev Ghai , Guy Lynn Guthrie , Stephen Powell , William John Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/0855 , G06F12/126
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。当L2高速缓存存储器完成对中断加载请求的服务时，L2高速缓冲存储器可以在中断点返回服务中断的存储请求。

179. 发明申请

US20100268886A1 SPECIFYING AN ACCESS HINT FOR PREFETCHING PARTIAL CACHE BLOCK DATA IN A CACHE HIERARCHY 失效
标题翻译：指定访问提示用于缓存高速缓存中的部分缓存块数据
公开(公告)号：US20100268886A1
公开(公告)日：2010-10-21
申请号：US12424716
申请日：2009-04-16
申请人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
发明人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0817 , G06F2212/6028
摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.
摘要翻译：用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。

180. 发明授权

US07469318B2 System bus structure for large L2 cache array topology with different latency domains 失效
标题翻译：具有不同延迟域的大二级缓存阵列拓扑的系统总线结构
公开(公告)号：US07469318B2
公开(公告)日：2008-12-23
申请号：US11054925
申请日：2005-02-10
申请人： Vicente Enrique Chung , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Vicente Enrique Chung , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0851 , Y02D10/13
摘要： A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses. The first data bus can be one of a plurality of data busses in a first data bus set, and the second data bus can be one of a plurality of data busses in a second data bus set. Two address busses (one for each data bus set) are used to receive successive address tags that identify which portions of the requested memory values are being received from each data bus set. For example, the requested memory values may be 32 bytes each, and the separate portions of the requested memory values are received over four successive cycles with an 8-byte portion of each value received each cycle. The cache lines are spread across different cache sectors of the cache memory, wherein the cache sectors have different output latencies, and the separate portions of a given requested memory value are loaded sequentially into the corresponding cache sectors based on their respective output latencies. Merge flow circuits responsive to the cache controller are used to receive the portions of a requested memory value and input those bytes into the cache sector.
摘要翻译：一种高速缓冲存储器，其通过在连续时钟周期的第一时间间隔内从第一数据总线接收第一请求存储器值的分开的部分来将两个存储器值加载到两个高速缓存行中，并且从第二数据接收第二请求存储器值的分离部分总线与第一时间跨度重叠的连续时钟周期的第二时间跨度。在说明性实施例中，第一输入线用于加载第一高速缓存行的第一字节数组和第二高速缓存行的第一字节数组，第二输入行用于加载第一高速缓存的第二字节数组线和第二高速缓存线的第二字节阵列，并且第一和第二存储器值的分离部分的传输在第一和第二数据总线之间交错。第一数据总线可以是第一数据总线组中的多个数据总线之一，并且第二数据总线可以是第二数据总线组中的多个数据总线中的一个。两个地址总线（每个数据总线集合一个）用于接收连续的地址标签，其识别从每个数据总线组接收到所请求的存储器值的哪些部分。例如，所请求的存储器值可以是每个32个字节，并且所请求的存储器值的分开的部分在四个连续周期中被接收，每个周期接收每个值的8字节部分。高速缓存行分布在高速缓冲存储器的不同高速缓存扇区上，其中高速缓存扇区具有不同的输出延迟，并且给定请求的存储器值的分离部分基于它们各自的输出延迟顺序地加载到相应的高速缓存扇区中。响应于高速缓存控制器的合并流回路用于接收请求的存储器值的部分并将这些字节输入高速缓存扇区。

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