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161. 发明申请

US20060242519A1 Multiple uses for bist test latches 失效
标题翻译：双重测试锁存器的多种用途
公开(公告)号：US20060242519A1
公开(公告)日：2006-10-26
申请号：US11101615
申请日：2005-04-07
申请人： Steven Ferguson , Garrett Koch , Osamu Takahashi , Michael White
发明人： Steven Ferguson , Garrett Koch , Osamu Takahashi , Michael White
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318536
摘要： A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.
摘要翻译：提供了一种方法，装置和计算机程序以利用用于多个目的的内置自检（BIST）锁存器。通常，BIST锁存器是单一目的。因此，单独的锁存器用于阵列内置自检（ABIST）和逻辑内置自检（LBIST）操作。然而，通过使用单独的锁存器，大量的区域丢失。因此，为了更好地利用锁存器和区域，ABIST锁存器被重新配置以利用一些以前未使用的端口来允许锁存器的多个使用，例如用于LBIST。

162. 发明授权

US07085147B2 Systems and methods for preventing malfunction of content addressable memory resulting from concurrent write and lookup operations 有权
标题翻译：用于防止由并发写入和查找操作导致的内容可寻址内存故障的系统和方法
公开(公告)号：US07085147B2
公开(公告)日：2006-08-01
申请号：US11003084
申请日：2004-12-03
申请人： Hiroaki Murakami , Hiromi Noro , Osamu Takahashi
发明人： Hiroaki Murakami , Hiromi Noro , Osamu Takahashi
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： Systems and methods for preventing the corruption of a CAM lookup result when a lookup in the CAM and a write to the CAM are concurrently executed. In one embodiment, a tag value is clocked into a tag latch simultaneously with a data value being clocked into a data latch. The tag value and initial CAM element values begin propagating through comparison logic. After a delay, the data value is written from the data latch to a CAM element. After the tag value and initial CAM values propagate through the comparison logic to produce comparison outputs, but before the newly written data value propagates through the comparison logic and changes the comparison outputs, the comparison outputs are latched. The comparison outputs can then be processed as if the data values in the CAM elements had not been changed by the write operation.
摘要翻译：当CAM中的查找和对CAM的写入被同时执行时，用于防止CAM查找的损坏的系统和方法。在一个实施例中，将标签值与被计入数据锁存器的数据值同时定时到标签锁存器中。标签值和初始CAM元素值通过比较逻辑开始传播。在延迟之后，将数据值从数据锁存器写入CAM元件。在标签值和初始CAM值通过比较逻辑传播以产生比较输出之后，但在新写入的数据值通过比较逻辑传播并更改比较输出之前，比较输出被锁存。然后可以像比较输出那样处理，因为CAM元素中的数据值没有被写入操作改变。

163. 发明申请

US20060166089A1 Battery pack 有权
标题翻译：电池组
公开(公告)号：US20060166089A1
公开(公告)日：2006-07-27
申请号：US11334217
申请日：2006-01-17
申请人： Fumihiko Suzuki , Osamu Takahashi , Hiroyuki Yamada , Kazuo Togashi , Toru Ishii , Takayuki Yamahira
发明人： Fumihiko Suzuki , Osamu Takahashi , Hiroyuki Yamada , Kazuo Togashi , Toru Ishii , Takayuki Yamahira
IPC分类号： H01M2/08 , H01M2/04
CPC分类号： H01M2/1061 , H01M2/0275 , H01M2/0287 , H01M10/0525 , H01M10/0565 , H01M10/4221 , H01M10/4257 , H01M10/448 , H01M2200/103 , H01M2200/106
摘要： A battery pack is provided. For example, the battery pack includes a box-shaped or plate-shaped battery pack. The battery pack has a hard outer jacket member, a box-shaped or plate-shaped battery element, a cover, and a circuit board. The hard outer jacket member has a first opening and a second opening formed at both ends. The box-shaped or plate-shaped battery element is contained in the outer jacket member and has electrode terminals. The cover is molded from resin and is fitted to the first opening. The circuit board is connected to the electrode terminal leads and contained in the cover. At least the electrode terminal leads extends from the first opening. The cover has concave portions on both ends of one longer side. The outer jacket member has cut portions that expose at least the concave portions of the cover. At least a longer side of the cover and the outer jacket member are heat-adhered.
摘要翻译：提供电池组。例如，电池组包括盒形或板状电池组。电池组具有硬的外护套构件，盒形或板状电池元件，盖和电路板。硬外护套构件具有形成在两端的第一开口和第二开口。盒状或板状电池元件容纳在外护套构件中并具有电极端子。盖子由树脂模制，并安装在第一个开口上。电路板连接到电极端子引线并包含在盖中。至少电极端子引线从第一开口延伸。盖在一个较长的一侧的两端具有凹部。外护套构件具有至少露出盖的凹部的切割部分。盖和外护套构件的至少较长一侧被热粘附。

164. 发明申请

US20060156090A1 Memory array manufacturing defect detection system and method 失效
标题翻译：内存阵列制造缺陷检测系统及方法
公开(公告)号：US20060156090A1
公开(公告)日：2006-07-13
申请号：US11002692
申请日：2004-12-02
申请人： Louis Bushard , Sang Dhong , Brian Flachs , Osamu Takahashi , Michael White
发明人： Louis Bushard , Sang Dhong , Brian Flachs , Osamu Takahashi , Michael White
IPC分类号： G11C29/00
CPC分类号： G11C29/08 , G11C7/20 , G11C2029/0407
摘要： The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and a logic built-in self test scan on the memory array is performed based on the identified deterministic read output function.
摘要翻译：本发明提供了一种用于存储器阵列校验的方法。接收初始化命令，并根据接收到的初始化命令生成内存阵列初始化设置。存储器阵列初始化设置存储在存储器阵列中。识别存储器阵列的确定性读输出功能，并且基于所识别的确定性读输出功能来执行存储器阵列上的逻辑内置自检扫描。

165. 发明申请

US20060152247A1 System and method for reducing power consumption associated with the capacitance of inactive portions of a multiplexer 有权
标题翻译：用于降低与多路复用器的非活动部分的电容相关联的功耗的系统和方法
公开(公告)号：US20060152247A1
公开(公告)日：2006-07-13
申请号：US11033612
申请日：2005-01-12
申请人： Hiroaki Murakami , Osamu Takahashi , Shoji Onishi
发明人： Hiroaki Murakami , Osamu Takahashi , Shoji Onishi
IPC分类号： H03K19/173
CPC分类号： H03K19/1737
摘要： Systems and methods for reducing the power consumption associated with the capacitance of sections of a multiplexer are disclosed. At each cycle, a timing signal is selectively sent only to sections of the multiplexer that include active logic. A plurality of control signals is received for processing by a corresponding plurality of input selection circuits. A plurality of additional inputs corresponding to the plurality of input selection circuits may also be received. In one embodiment, each input selection circuit is configured to output a corresponding input signal if a corresponding control signal is asserted and a timing signal is made available to the input selection circuit. To avoid unnecessary power consumption associated with the capacitance of various portions of the multiplexer, the timing signal is only asserted to a portion of the multiplexer at any given clock cycle according to the values of the control signals.
摘要翻译：公开了用于降低与多路复用器的部分的电容相关联的功耗的系统和方法。在每个周期，定时信号仅选择性地仅发送到包括有效逻辑的多路复用器的部分。多个控制信号被接收用于由相应的多个输入选择电路进行处理。还可以接收对应于多个输入选择电路的多个附加输入。在一个实施例中，每个输入选择电路被配置为如果相应的控制信号被断言并且使定时信号对输入选择电路可用，则输出相应的输入信号。为了避免与多路复用器的各个部分的电容相关联的不必要的功率消耗，定时信号仅根据控制信号的值以任何给定的时钟周期被认定到多路复用器的一部分。

166. 发明授权

US07053668B2 SOI sense amplifier with cross-coupled body terminal 有权
标题翻译：具有交叉耦合体端子的SOI读出放大器
公开(公告)号：US07053668B2
公开(公告)日：2006-05-30
申请号：US10852863
申请日：2004-05-25
申请人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
发明人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
IPC分类号： G01R19/00 , G11C7/00 , H03F3/45
CPC分类号： H03K3/012 , G11C7/065 , H03K3/356139
摘要： Systems and methods for increasing the amount of current that can flow through the data line pull-down transistors in a sense amplifier by tying the bodies of these transistors to a voltage other than ground. In one embodiment, the bodies of the data line pull-down transistors in a sense amplifier are tied to the intermediate nodes on the opposing side of the sense amplifier to increase the current flow through the data line pull-down transistors, and also to reduce the voltage at the intermediate node that will be pulled low by the action of the bit line transistors. In one embodiment, the sense amplifier also includes pre-charge circuits which pre-charge the intermediate nodes to a predetermined voltage that is not reduced by the threshold voltage of the pull-down transistors.
摘要翻译：用于通过将这些晶体管的主体连接到除地之外的电压来增加可以流过读出放大器中的数据线下拉晶体管的电流量的系统和方法。在一个实施例中，读出放大器中的数据线下拉晶体管的主体被连接到读出放大器的相对侧上的中间节点，以增加通过数据线下拉晶体管的电流，并且还减少通过位线晶体管的动作将中间节点处的电压拉低。在一个实施例中，读出放大器还包括将中间节点预充电到未被下拉晶体管的阈值电压降低的预定电压的预充电电路。

167. 发明授权

US07030658B2 Systems and methods for operating logic circuits 有权
标题翻译：用于操作逻辑电路的系统和方法
公开(公告)号：US07030658B2
公开(公告)日：2006-04-18
申请号：US10764179
申请日：2004-01-23
申请人： Hiroaki Murakami , Osamu Takahashi , Jieming Qi
发明人： Hiroaki Murakami , Osamu Takahashi , Jieming Qi
IPC分类号： H03K19/20
CPC分类号： H03K19/1737 , H03K19/0016
摘要： Systems and methods for reducing the power consumption of some combinations of logic gates by reducing the number of unnecessary transitions that are made by logic gates that do not affect the output of the logic. In one embodiment, a modified exclusive-OR (XOR) gate is coupled to a modified multiplexer. The XOR gate has two inputs, Ain and Bin, and an output, XORout, which is provided as an input to the multiplexer. Another input to the multiplexer is Cin. A select signal is input to the multiplexer to select either Cin or XORout to be provided at the output of the multiplexer. If XORout is selected, the XOR gate operates in a first mode in which it functions as a normal XOR gate. If Cin is selected, the XOR gate operates in a second mode in which the XOR gate uses less power than when the XOR gate operates normally.
摘要翻译：通过减少不影响逻辑输出的逻辑门进行的不必要的转换次数来减少逻辑门的某些组合的功耗的系统和方法。在一个实施例中，修改的异或（XOR）门耦合到修改的多路复用器。 XOR门具有两个输入，即中的和B _{中的A _{和作为多路复用器的输入提供的输出XOR < 。复用器的另一个输入是中的C _{。选择信号被输入到多路复用器以选择要在多路复用器的输出处提供的或XOR _{输出中的C _{。如果选择XOR ，则异或门以第一模式工作，其中它用作正常的异或门。如果选择了中的C ，则异或门以第二模式工作，其中XOR门比XOR门正常工作时使用的功率更小。}}}}}

168. 发明授权

US06973010B1 Timepiece device 失效
标题翻译：钟表装置
公开(公告)号：US06973010B1
公开(公告)日：2005-12-06
申请号：US09830519
申请日：2000-08-23
申请人： Nobuhiro Koike , Mamoru Miyasaka , Osamu Takahashi
发明人： Nobuhiro Koike , Mamoru Miyasaka , Osamu Takahashi
IPC分类号： G04C3/00 , G04C10/00 , G04C13/11 , H02K3/18 , H02K37/16 , H02K37/00
CPC分类号： G04C13/11 , G04C3/008 , G04C10/00 , H02K3/18 , H02K37/16
摘要： In a generator 120 in an electronic-controlled mechanical timepiece, the winding core 133b of a coil 134 arranged nearer to the perimeter of a base plate 2 is made shorter than the winding core 123b of a coil 124 arranged more inside. Accordingly, it is possible to make the area of an opening 2c can be made smaller in comparison with the prior art, and make the timepiece more small-sized by making smaller the outer diameter of the base plate 2 as keeping the distance D1 between the corner part of the opening 2c and the perimeter of the base plate 2 to the same degree as the prior art and thereby securing the strength of the base plate 2.
摘要翻译：在电子机械钟表的发电机120中，布置得更靠近基板2的周边的线圈134的卷绕芯133b比布置在内侧的线圈124的卷绕芯123b短。因此，与现有技术相比，可以使开口部2c的面积变小，通过使基板2的外径保持距离D 1更小，使钟表体积更小在开口部2c的角部与基板2的周边之间，与现有技术的程度相同，由此确保基板2的强度。

169. 发明申请

US20050264322A1 SOI sense amplifier with pre-charge 审中-公开
标题翻译：具有预充电的SOI读出放大器
公开(公告)号：US20050264322A1
公开(公告)日：2005-12-01
申请号：US10852868
申请日：2004-05-25
申请人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
发明人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
IPC分类号： G11C11/419 , G11C7/06 , G11C7/12 , H03F3/45 , H03K3/356 , H03K19/0948
CPC分类号： G11C7/065 , G11C7/12 , H03F3/45183 , H03F2203/45318
摘要： Systems and methods for pre-charging opposing nodes in a sense amplifier to substantially the same voltage in order to reduce or eliminate malfunctions arising from differences in threshold voltages of transistors coupled to the opposing nodes. One embodiment is a method including providing a silicon-on-insulator (SOI) sense amplifier having intermediate nodes between the transistors coupling each output data line to the corresponding input bit line and pre-charging each intermediate node to a predetermined voltage while the sense amplifier is not enabled. In one embodiment, the intermediate nodes are pre-charged by coupling them to a voltage source through pre-charge paths that do not include the data line pull-down transistors. In one embodiment, the method also includes decoupling the pre-charge paths after pre-charging the intermediate nodes and then enabling the sense amplifier.
摘要翻译：用于将读出放大器中的相对节点预充电到基本相同的电压的系统和方法，以便减少或消除由耦合到相对节点的晶体管的阈值电压的差异引起的故障。一个实施例是一种方法，包括提供绝缘体上硅（SOI）读出放大器，该晶体管在晶体管之间具有中间节点，每个晶体管将每个输出数据线耦合到相应的输入位线，并将每个中间节点预充电到预定电压，而读出放大器未启用在一个实施例中，中间节点通过不包括数据线下拉晶体管的预充电路径将其耦合到电压源进行预充电。在一个实施例中，该方法还包括在对中间节点预充电然后启用读出放大器之后去耦合预充电路径。

170. 发明申请

US20050261395A1 Ink composition and inkjet recording method 审中-公开
标题翻译：油墨成分和喷墨记录方法
公开(公告)号：US20050261395A1
公开(公告)日：2005-11-24
申请号：US11125406
申请日：2005-05-10
申请人： Takahiro Ishizuka , Toshiki Fujiwara , Osamu Takahashi , Junichi Yamanouchi , Yoshiharu Yabuki
发明人： Takahiro Ishizuka , Toshiki Fujiwara , Osamu Takahashi , Junichi Yamanouchi , Yoshiharu Yabuki
IPC分类号： C09D11/00 , C03C17/00
CPC分类号： C09D11/32
摘要： To provide an ink composition that when printed using a nozzle, does not cause clogging at the chip of the nozzle, is free from paper dependency, and when printed on an arbitrarily chosen paper, exhibits superior properties in water resistance, scratch resistance, lightfastness and ozone resistance and an inkjet recording method using it. The ink composition contains colored fine particles containing an oil-soluble polymer and an oil-soluble dye having an oxidation potential higher than 1.0 V (vs SCE), in an aqueous medium.
摘要翻译：为了提供当使用喷嘴打印时不会在喷嘴的芯片处产生堵塞的油墨组合物，没有纸张依赖性，并且当印刷在任意选择的纸张上时，在耐水性，耐刮擦性，耐光性和耐臭氧性和使用它的喷墨记录方法。油墨组合物含有在水性介质中含有油溶性聚合物和氧化电位高于1.0V（相对于SCE）的油溶性染料的着色微粒。

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