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151. 发明授权

US06734063B2 Non-volatile memory cell and fabrication method 有权
标题翻译：非易失性存储单元及其制造方法
公开(公告)号：US06734063B2
公开(公告)日：2004-05-11
申请号：US10200423
申请日：2002-07-22
申请人： Josef Willer , Franz Hofmann , Armin Kohlhase , Christoph Ludwig
发明人： Josef Willer , Franz Hofmann , Armin Kohlhase , Christoph Ludwig
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： Memory cell transistors with back-channel isolation are produced without using an SOI substrate. With the word line stack acting as a mask, the semiconductor material is etched on both sides of the world line, first anisotropically and then isotropically to widen the etch hole and form an undercut beneath the gate electrode and at a distance from the ONO storage layer forming the gate dielectric. The undercut is filled, whereby a buried oxide layer of at least 20 nm maximum thickness is formed underneath the channel region. The latter is p-doped at a density of at least 1017 cm−3.
摘要翻译：在不使用SOI衬底的情况下制造具有背沟道隔离的存储单元晶体管。利用字线叠层作为掩模，半导体材料在世界线的两侧蚀刻，首先各向异性地，然后各向同性地加宽蚀刻孔，并在栅电极下方并在与ONO存储层一定距离处形成底切形成栅极电介质。填充底切，由此在通道区域的下方形成最大厚度为至少20nm的掩埋氧化物层。后者以至少10 17 cm -3的密度进行p掺杂。

152. 发明授权

US06673677B2 Method for manufacturing a multi-bit memory cell 有权
标题翻译：多位存储单元的制造方法
公开(公告)号：US06673677B2
公开(公告)日：2004-01-06
申请号：US10352826
申请日：2003-01-28
申请人： Franz Hofmann , Josef Willer
发明人： Franz Hofmann , Josef Willer
IPC分类号： H01L21336
CPC分类号： H01L29/66833 , H01L29/7923 , Y10S438/954
摘要： A memory layer intended for trapping charge carriers over a source region and a drain region is interrupted over the channel so that a diffusion of the charge carriers, which are trapped over the source region and over the drain region, is prevented. The memory layer is limited to regions over the parts of the source region and of the drain region facing the channel and is embedded all around in oxide.
摘要翻译：用于在源极区域和漏极区域上捕获电荷载流子的存储层在沟道上被中断，从而防止了俘获在源极区域和漏极区域上方的电荷载流子的扩散。存储层被限制在源区域和漏极区域的面向通道的部分上的区域，并且被全部包埋在氧化物中。

153. 发明授权

US06566182B2 DRAM memory cell for DRAM memory device and method for manufacturing it 有权
标题翻译：用于DRAM存储器件的DRAM存储单元及其制造方法
公开(公告)号：US06566182B2
公开(公告)日：2003-05-20
申请号：US09875803
申请日：2001-06-06
申请人： Franz Hofmann , Till Schlosser
发明人： Franz Hofmann , Till Schlosser
IPC分类号： H01L218238
CPC分类号： H01L27/10858 , H01L27/1082 , H01L27/10823 , H01L27/10876 , H01L27/1203
摘要： A DRAM memory cell includes a MOSFET selection transistor having a drain region and a source region in a semiconductor substrate column. A current channel, which is capable of being actuated by a control gate electrode extends in a vertical direction between the drain and source regions. A capacitor is stacked under the selection transistor and electrically connected to the source region in the semiconductor substrate column. Above the selection transistor is a metal bit line electrically connected to the drain region in the semiconductor substrate column. A metal word line in direct electrical communication with the control gate electrode of the selection transistor extends perpendicularly with respect to the metal bit line.
摘要翻译： DRAM存储单元包括在半导体衬底列中具有漏极区域和源极区域的MOSFET选择晶体管。能够由控制栅极电极驱动的电流通道在漏极和源极区域之间沿垂直方向延伸。电容器层叠在选择晶体管的下方并与半导体衬底列中的源极区域电连接。在选择晶体管上方是与半导体衬底列中的漏极区域电连接的金属位线。与选择晶体管的控制栅电极直接电连通的金属字线相对于金属位线垂直地延伸。

154. 发明授权

US06469335B2 Semiconductor memory having a memory cell array 有权
标题翻译：具有存储单元阵列的半导体存储器
公开(公告)号：US06469335B2
公开(公告)日：2002-10-22
申请号：US09820234
申请日：2001-03-28
申请人： Franz Hofmann
发明人： Franz Hofmann
IPC分类号： H01L27108
CPC分类号： H01L27/10873 , H01L27/092 , H01L27/10808 , H01L27/10829 , H01L27/10841
摘要： A semiconductor memory such as, for example, a DRAM (Dynamic Random Access Memory) includes a memory cell array and an addressing periphery. A first memory cell having a first selection transistor and a first storage capacitor, and a second memory cell having a second selection transistor and a second storage capacitor are configured in the memory cell array. The first selection transistor is designed as an n-channel transistor and the second selection transistor is designed as a p-channel transistor. This makes it possible to realize a folded bit line concept for memory cells which are smaller than 8F2.
摘要翻译：诸如例如DRAM（动态随机存取存储器）的半导体存储器包括存储单元阵列和寻址周边。具有第一选择晶体管和第一存储电容器的第一存储单元以及具有第二选择晶体管和第二存储电容器的第二存储单元配置在存储单元阵列中。第一选择晶体管被设计为n沟道晶体管，第二选择晶体管被设计为p沟道晶体管。这使得可以实现小于8F2的存储单元的折叠位线概念。

155. 发明授权

US06420228B1 Method for the production of a DRAM cell configuration 有权
标题翻译：用于生产DRAM单元配置的方法
公开(公告)号：US06420228B1
公开(公告)日：2002-07-16
申请号：US09851051
申请日：2001-05-08
申请人： Wolfgang Roesner , Lothar Risch , Franz Hofmann
发明人： Wolfgang Roesner , Lothar Risch , Franz Hofmann
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A DRAM cell configuration includes a vertical MOS transistor per memory cell. First source/drain regions of the transistor each belong to two adjacent transistors and adjoin a bit line. Second source/drain regions of the transistor are connected to a storage node. A gate electrode of the transistor has exactly two sides adjoined by a gate oxide. The DRAM cell configuration can be produced by using three masks with a memory cell area of 4 F2. F is a minimum structure size which can be produced by using the respective technology.
摘要翻译： DRAM单元配置包括每个存储单元的垂直MOS晶体管。晶体管的第一源极/漏极区域分别属于两个相邻的晶体管并与位线相邻。晶体管的第二源/漏区连接到存储节点。晶体管的栅电极具有由栅极氧化物邻接的正好两侧。可以通过使用具有4F2的存储单元面积的三个掩模来产生DRAM单元配置。 F是可以通过使用各自技术制造的最小结构尺寸。

156. 发明授权

US6040995A Method of operating a storage cell arrangement 失效
标题翻译：操作存储单元布置的方法
公开(公告)号：US6040995A
公开(公告)日：2000-03-21
申请号：US230614
申请日：1999-01-28
申请人： Hans Reisinger , Ulrike Gruning , Hermann Wendt , Reinhard Stengl , Volker Lehmann , Josef Willer , Martin Franosch , Herbert Schafer , Wolfgang Krautschneider , Franz Hofmann , Thomas Bohm
发明人： Hans Reisinger , Ulrike Gruning , Hermann Wendt , Reinhard Stengl , Volker Lehmann , Josef Willer , Martin Franosch , Herbert Schafer , Wolfgang Krautschneider , Franz Hofmann , Thomas Bohm
IPC分类号： H01L21/8247 , H01L29/51 , H01L29/788 , H01L29/792 , H01L27/02
CPC分类号： H01L29/513 , H01L29/518 , H01L29/792
摘要： For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.
摘要翻译： PCT No.PCT / DE97 / 01601 Sec。 371日期1999年1月28日 102（e）1999年1月28日PCT PCT 1997年7月29日PCT公布。出版物WO98 / 06140 日期1998年2月12日对于具有MOS晶体管的存储单元布置的操作，作为包含具有第一氧化硅层（51）的介电三层（5）的存储单元，具有氮化硅层（52）和第二氧化硅层（53）作为栅极电介质，由此氧化硅层分别为至少3nm厚，将第一截止电压值分配给第一逻辑值，并将MOS晶体管的第二截止电压值分配给第二逻辑值用于存储数字数据。存储在存储单元中的信息可以通过施加相应的电压电平来修改，尽管由于氧化硅层的厚度，不可能完全去除存储在氮化硅层中的电荷。当修改截止电压时，利用的是电介质三层中的电场由存储在氮化硅层中的电荷而失真。

157. 发明授权

US5882969A Method for manufacturing an electrically writeable and erasable read-only memory cell arrangement 失效
标题翻译：用于制造电可写和可擦除的只读存储单元布置的方法
公开(公告)号：US5882969A
公开(公告)日：1999-03-16
申请号：US967419
申请日：1997-11-11
申请人： Wolfgang Krautschneider , Franz Hofmann , Hans Reisinger , Josef Willer
发明人： Wolfgang Krautschneider , Franz Hofmann , Hans Reisinger , Josef Willer
IPC分类号： H01L21/822 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L21/336 , H01L29/78
CPC分类号： H01L27/11521 , H01L21/8221 , H01L27/11551
摘要： In a method for manufacturing an electrically writeable and erasable ad-only memory cell arrangement, by self-adjusting process steps, a read-only memory cell arrangement having memory cells that respectively comprise an MOS transistor with a floating gate is manufactured. The MOS transistors are arranged in rows that run parallel. Adjacent rows thus respectively run alternately on the bottom of longitudinal trenches and between adjacent longitudinal trenches. The control gates laterally surround the floating gates so that the memory cells on the bottom of the longitudinal trenches also comprise a coupling ratio>1. A surface requirement per memory cell of 2F.sup.2 (F minimum structural size) is achieved.
摘要翻译：在通过自调整处理步骤制造电可写和可擦除的仅ad的存储单元布置的方法中，制造了具有分别包括具有浮置栅极的MOS晶体管的存储单元的只读存储单元布置。 MOS晶体管排列成并行的行。因此，相邻的行分别在纵向沟槽的底部和相邻的纵向沟槽之间交替地行进。控制门横向围绕浮动栅极，使得纵向沟槽底部的存储单元也包括耦合比> 1。实现2F2（F最小结构尺寸）每个存储单元的表面要求。

158. 发明授权

US5744393A Method for production of a read-only-memory cell arrangement having vertical MOS transistors 失效
标题翻译：用于制造具有垂直MOS晶体管的只读存储单元布置方法
公开(公告)号：US5744393A
公开(公告)日：1998-04-28
申请号：US836175
申请日：1997-04-17
申请人： Lothar Risch , Franz Hofmann , Wolfgang Rosner , Wolfgang Krautschneider
发明人： Lothar Risch , Franz Hofmann , Wolfgang Rosner , Wolfgang Krautschneider
IPC分类号： H01L21/8234 , H01L21/8246 , H01L27/088 , H01L27/112 , H01L29/739 , H01L29/78
CPC分类号： H01L27/112
摘要： A method for production of a read-only-memory cell arrangement having vertical MOS transistors is provided. In order to produce a read-only-memory cell arrangement which has first memory cells having a vertical MOS transistor and second memory cells which do not have a vertical MOS transistor, holes provided with a gate dielectric and a gate electrode are etched in a silicon substrate with a layer sequencing corresponding to a source, a channel and a drain for the first memory cells. Insulation trenches whose separation is preferably equal to their width are produced for insulation of adjacent memory cells.
摘要翻译： PCT No.PCT / DE95 / 01365 Sec。 371日期1997年04月17日 102（e）日期1997年4月17日PCT提交1995年10月5日PCT公布。出版物WO96 / 13064 日期：1996年5月2日提供具有垂直MOS晶体管的只读存储单元布置方法。为了产生具有垂直MOS晶体管的第一存储单元和不具有垂直MOS晶体管的第二存储单元的只读存储单元布置，在栅极电介质和栅电极中设置的孔被蚀刻在硅具有对应于第一存储器单元的源极，沟道和漏极的层序列的衬底。为了绝缘相邻的存储单元而产生绝缘沟槽，其隔离优选等于其宽度。

159. 发明授权

US08492844B2 Fully depleted SOI device with buried doped layer 有权
标题翻译：具有掩埋掺杂层的完全耗尽的SOI器件
公开(公告)号：US08492844B2
公开(公告)日：2013-07-23
申请号：US13305206
申请日：2011-11-28
申请人： Gerhard Enders , Wolfgang Hoenlein , Franz Hofmann , Carlos Mazure
发明人： Gerhard Enders , Wolfgang Hoenlein , Franz Hofmann , Carlos Mazure
IPC分类号： H01L27/088 , H01L29/36 , H01L21/8238
CPC分类号： H01L27/10894 , H01L21/84 , H01L27/10876 , H01L27/1207 , H01L29/4236 , H01L29/66621
摘要： The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.
摘要翻译：本发明涉及通过提供第一基板来制造半导体器件的方法; 在所述第一衬底的表面区域中提供掺杂层; 在所述掺杂层上提供掩埋氧化物层; 在掩埋氧化物层上提供半导体层以获得绝缘体上半导体（SeOI）晶片; 从所述SeOI晶片的第一区域去除所述掩埋氧化物层和所述半导体层，同时将所述掩埋氧化物层和所述半导体层保持在所述SeOI晶片的第二区域中; 通过在掺杂层中或由掺杂层形成背栅，在第二区域中提供上晶体管; 以及通过在掺杂层中或由掺杂层形成源极和漏极区域来在第一区域中提供下部晶体管。

160. 发明授权

US08241989B2 Integrated circuit with stacked devices 有权
标题翻译：集成电路与堆叠器件
公开(公告)号：US08241989B2
公开(公告)日：2012-08-14
申请号：US12271313
申请日：2008-11-14
申请人： Franz Hofmann
发明人： Franz Hofmann
IPC分类号： H01L21/76
CPC分类号： H01L27/11524 , H01L21/8221 , H01L27/0688 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/11551 , H01L27/11578
摘要： An integrated circuit with stacked devices. One embodiment provides a surface of a first semiconductor structure of a first crystalline semiconductor material including first and second portions. First structures are formed on the first portions. The second portions remain uncovered. Sacrificial structures of a second, different crystalline material are formed on the second portions. A second semiconductor structure of the first crystalline semiconductor material is formed over the sacrificial structures and over the first structures.
摘要翻译：集成电路与堆叠器件。一个实施例提供包括第一和第二部分的第一晶体半导体材料的第一半导体结构的表面。在第一部分上形成第一结构。第二部分保持未被覆盖。在第二部分上形成第二不同结晶材料的牺牲结构。第一晶体半导体材料的第二半导体结构形成在牺牲结构之上和第一结构上。

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