专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

141. 发明申请

US20050212975A1 Television signal transmitter capable of reducing phase noise 审中-公开
标题翻译：电视信号发射机能够降低相位噪声
公开(公告)号：US20050212975A1
公开(公告)日：2005-09-29
申请号：US11087276
申请日：2005-03-22
申请人： Yasuharu Kudo
发明人： Yasuharu Kudo
IPC分类号： H04N5/38 , H03D7/16 , H03L7/16 , H03L7/197 , H04B1/04
CPC分类号： H04N5/4446 , H03D7/163 , H03L7/16 , H04N5/38
摘要： A television signal transmitter containing: a first frequency conversion unit for up-converting a first intermediate frequency signal modulated by an image signal and a voice signal into a second intermediate frequency signal and a second frequency conversion unit for down-converting the second intermediate frequency signal into a television channel signal. The first frequency conversion unit is provided with a first local oscillating circuit and a first PLL circuit for controlling an oscillating frequency of the first local oscillating circuit. The second frequency conversion unit is provided with a second local oscillating circuit and a second PLL circuit for controlling an oscillating frequency of the second local oscillating circuit. The first PLL circuit and the second PLL circuit are constituted by fractional PLL circuits, respectively.
摘要翻译：一种电视信号发送器，包括：第一频率转换单元，用于将由图像信号调制的第一中频信号和语音信号上变频为第二中频信号;第二频率转换单元，用于将第二中频信号进入电视频道信号。第一变频单元设置有第一本地振荡电路和用于控制第一本地振荡电路的振荡频率的第一PLL电路。第二变频单元设置有用于控制第二本地振荡电路的振荡频率的第二本地振荡电路和第二PLL电路。第一PLL电路和第二PLL电路分别由分数PLL电路构成。

142. 发明授权

US06940937B2 Scalable high-speed precision frequency and phase synthesis 有权
标题翻译：可扩展的高速精密频率和相位合成
公开(公告)号：US06940937B2
公开(公告)日：2005-09-06
申请号：US10026489
申请日：2001-12-24
申请人： Liming Xiu , Zhihong You
发明人： Liming Xiu , Zhihong You
IPC分类号： H03K5/00 , H03L7/099 , H03L7/16 , H03D3/24
CPC分类号： H03L7/16 , H03K2005/00208 , H03L7/0996
摘要： A clock synthesis circuit (22) including a phase-locked loop (25) and one or more frequency synthesis circuits (27; 77; 227; 237) is disclosed. A disclosed implementation of the phase-locked loop (25) includes a voltage-controlled oscillator (30) having an even number of differential stages (31) to produce an even number of equally spaced clock phases. In one arrangement, the frequency synthesis circuit (27) includes two adder legs that generate select signals applied to first and second multiplexers (40a, 40b), for selecting among the clock phases from the voltage-controlled oscillator (30). The outputs of the first and second multiplexers (40a, 40b) are applied to a two-to-one multiplexer (46) which is controlled by the output clock signal (CLK1), to drive clock edges to a T flip-flop (48) to produce the output clock signals (CLK1, CLK2). In another embodiment, more than two adder and register units (55) control corresponding multiplexers (56) for selecting clock phases from the voltage-controlled oscillator (30) for application to an output multiplexer (58), which is controlled by a clock control circuit (60) to apply the selected clock phases to the T flip-flop (62). In another embodiment, primary and phase-shifted frequency synthesis circuits (227, 327) receive initialization values (INIT1, INIT2) that establish the phase differential and ensure proper initialization.
摘要翻译：公开了一种包括锁相环（25）和一个或多个频率合成电路（27; 77; 227; 237）的时钟合成电路（22）。所公开的锁相环（25）的实现包括具有偶数个差分级（31）的压控振荡器（30），以产生偶数等间隔的时钟相位。在一种布置中，频率合成电路（27）包括两个加法器支路，其产生施加到第一和第二多路复用器（40a，40b）的选择信号，用于在来自压控振荡器（30）的时钟相位之间进行选择。第一和第二多路复用器（40a，40b）的输出被施加到由输出时钟信号（CLK 1）控制的二对一复用器（46），以将时钟边缘驱动到T触发器（48）以产生输出时钟信号（CLK 1，CLK 2）。在另一实施例中，多于两个的加法器和寄存器单元（55）控制相应的多路复用器（56），用于从压控振荡器（30）中选择时钟相位，用于施加到输出多路复用器（58），其由时钟控制电路（60）将所选择的时钟相位施加到T触发器（62）。在另一个实施例中，初级和相移频率合成电路（227,327）接收建立相位差并初始化的初始化值（INIT 1，INIT 2）。

143. 发明授权

US06934731B1 Rational frequency synthesizers employing digital commutators 有权
标题翻译：采用数字换向器的合理频率合成器
公开(公告)号：US06934731B1
公开(公告)日：2005-08-23
申请号：US09579847
申请日：2000-05-25
申请人： Ron D. Katznelson
发明人： Ron D. Katznelson
IPC分类号： H03L7/08 , H03L7/16 , G06F1/02
CPC分类号： H03L7/16
摘要： A method and an apparatus are disclosed for digital synthesis of signals having a frequency which is a rational factor n/m times an existing reference or clock frequency, wherein n and m may be large relatively prime integers. The invention provides for the use of a periodic sequence generator having up to N taps which are connected to a cascade of digital commutating multiplexers. The periodic sequence generator and the commutating multiplexers have periodicities fi that are determined by programmable address counters and the choice of N. The resultant signal at the output of the last commutator stage has a spectral frequency component at a desired frequency which is an algebraic sum of the frequencies fi (each taken with either positive or negative signs). One aspect of the invention provides for the use of weighted linear combination of commutator output lines, thereby further aiding in improving its spectral purity performance. The advantage of the embodiments according to the invention is that it incurs very little phase noise degradations, thereby providing for a signal source with phase noise performance essentially equal to that of the reference signal.
摘要翻译：公开了一种用于数字合成信号的方法和装置，该信号的频率是现有参考或时钟频率的n / m倍的理性因子，其中n和m可以是相对较大的整数。本发明提供了使用具有多达N个抽头的周期性序列发生器，其连接到级联的数字换向多路复用器。周期序列发生器和换向多路复用器具有由可编程地址计数器确定的周期性和N的选择。在最后一个换向器级的输出处的所得到的信号具有频谱分量期望频率，其是频率f i i i的代数和（每个采用正或负符号）。本发明的一个方面提供了使用换向器输出线的加权线性组合，从而进一步有助于提高其光谱纯度性能。根据本发明的实施例的优点是它引起非常少的相位噪声降级，由此提供具有基本上等于参考信号的相位噪声性能的信号源。

144. 发明授权

US06933761B2 Techniques for dynamically selecting phases of oscillator signals 有权
标题翻译：用于动态选择振荡器信号相位的技术
公开(公告)号：US06933761B2
公开(公告)日：2005-08-23
申请号：US10600120
申请日：2003-06-20
申请人： Richard Chang
发明人： Richard Chang
IPC分类号： H03H11/16 , H03K3/00 , H03K5/00 , H03K5/13 , H03L7/081 , H03L7/099 , H03L7/16 , H03L7/18
CPC分类号： H03L7/0812 , H03K5/13 , H03K2005/00156 , H03K2005/00286 , H03L7/0996 , H03L7/16 , H03L7/18
摘要： Techniques for dynamically shifting the phase of clock signals are provided. A circuit generates a plurality of periodic clock signals. Each clock signal has the same period, the same duty cycle, and a different phase. The clock signals are provided to the inputs of two multiplexers. The output signals of the multiplexers are transmitted to a phase selection circuit that generations phase selection signals. The multiplexers each select one of the clock signals in response to the phase selection signals. When the phase selection signals change value, each multiplexer selects a different clock signal in order to shift the phase of its output signal forward or backward by an incremental value. A directional signal determines whether the multiplexers shift the phases of their output signals forward or backward in time.
摘要翻译：提供了用于动态地移动时钟信号的相位的技术。电路产生多个周期性时钟信号。每个时钟信号具有相同的周期，相同的占空比和不同的相位。时钟信号被提供给两个多路复用器的输入端。复用器的输出信号被发送到相位选择电路，该相位选择电路代表相位选择信号。多路复用器响应于相位选择信号而选择一个时钟信号。当相位选择信号改变值时，每个多路复用器选择不同的时钟信号，以将其输出信号的相位向前或向后移位增量值。定向信号确定多路复用器是否在时间上向前或向后移位其输出信号的相位。

145. 发明申请

US20050168260A1 Configurable delay line circuit 审中-公开
标题翻译：可配置延迟线电路
公开(公告)号：US20050168260A1
公开(公告)日：2005-08-04
申请号：US10767088
申请日：2004-01-29
申请人： Andrew Tomerlin , Robert Stengel
发明人： Andrew Tomerlin , Robert Stengel
IPC分类号： H03H11/26 , H03K5/00 , H03K5/13 , H03L7/08 , H03L7/081 , H03L7/16
CPC分类号： H03L7/0802 , H03K5/133 , H03K2005/00019 , H03L7/0812 , H03L7/0814 , H03L7/16
摘要： A configurable circuit consistent with certain embodiments has a variable length delay line (10), the delay line (10) having an input (24) and having N delay elements (12, 14, 16, 18, . . . , 20) to provide a plurality of N delayed outputs (T(0) through T(N)). The variable length delay line (10) also has a number of active delay elements determined by a program command. A configurable processing array (32) receives the delayed outputs from the active delay elements and secondary data (38). The configurable processing array has an array of configurable circuit elements (104, 130, 150). The configurable processing array is configured to process the delayed outputs and the secondary data (38) in a manner for which the invention is to be used. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
摘要翻译：与某些实施例一致的可配置电路具有可变长度延迟线（10），延迟线（10）具有输入（24）并且具有N个延迟元件（12,14,16,18 ... 20）提供多个N个延迟输出（T（0）至T（N））。可变长度延迟线（10）还具有由程序命令确定的多个有效延迟元件。可配置处理阵列（32）从主动延迟元件和辅助数据（38）接收延迟的输出。可配置处理阵列具有可配置电路元件（104,130,150）的阵列。可配置处理阵列被配置为以将要使用本发明的方式处理延迟的输出和辅助数据（38）。该摘要不被认为是限制性的，因为其他实施例可能偏离本摘要中描述的特征。

146. 发明授权

US06922110B2 Phase locked loop (PLL) frequency synthesizer and method 有权
标题翻译：锁相环（PLL）频率合成器和方法
公开(公告)号：US06922110B2
公开(公告)日：2005-07-26
申请号：US10884254
申请日：2004-07-02
申请人： Danny F. Ammar , Ronald D. Graham
发明人： Danny F. Ammar , Ronald D. Graham
IPC分类号： H03L7/23 , H03L7/07 , H03L7/16
CPC分类号： H03L7/23
摘要： A phase locked loop (PLL) frequency synthesizer generates a high frequency signal by generating an output signal from a voltage controlled oscillator of a primary phase locked loop (PLL) circuit. The voltage controlled oscillator output is programmably divided with a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency. An external reference signal used for the primary phase locked loop circuit is isolated by generating a voltage controlled, clean reference signal and filtering and synchronizing the clean reference signal with the external reference signal within a secondary phase locked loop circuit to produce the reference signal output to the primary phase locked loop circuit.
摘要翻译：锁相环（PLL）频率合成器通过从主锁相环（PLL）电路的压控振荡器产生输出信号来产生高频信号。压控振荡器输出可编程地以分频比的参考信号输出分频，使得输出等于公共相位比较频率。用于主锁相环电路的外部参考信号通过产生电压控制的干净的参考信号并将干净的参考信号与辅助锁相环电路中的外部参考信号进行滤波和同步来产生参考信号输出而被隔离主要锁相环电路。

147. 发明授权

US06917224B2 Frequency synthesizer and frequency synthesizing method 有权
标题翻译：频率合成器和频率合成方法
公开(公告)号：US06917224B2
公开(公告)日：2005-07-12
申请号：US10762518
申请日：2004-01-23
申请人： Yun-Cheol Han
发明人： Yun-Cheol Han
IPC分类号： H03L7/16 , H03K3/03 , H03K5/156 , H03B21/00
CPC分类号： H03K3/0322 , H03K5/1565
摘要： Provided are a frequency synthesizer and a frequency synthesizing method. The frequency synthesizer includes a ring oscillator, duty buffers, half adders, and a switch. The ring oscillator receives a pair of input signals and generates a pair of oscillating signals. The duty buffers receive the pair of oscillating signals of the ring oscillator and generates output signals with predetermined duty cycles. The half adders receive output signals of the duty buffers and generate an output signal as a result of an Exclusive-OR operation on the output signals of the duty buffers and an output signal as a result of an AND operation on the output signals of the duty buffers. The switch selects one of the oscillating signals of the ring oscillator, the output signals as results of the Exclusive-OR operation, and the output signals as results of the AND operation. By using the frequency synthesizer, it is possible to select one of an oscillating-frequency output signal of a high-frequency ring oscillator, an output signal of a high-frequency that is two times higher than that of the oscillating frequency of the ring oscillator bock, and an output signal of a frequency that is the same as that of an input signal.
摘要翻译：提供了一种频率合成器和频率合成方法。频率合成器包括环形振荡器，占空比缓冲器，半加法器和开关。环形振荡器接收一对输入信号并产生一对振荡信号。占空比缓冲器接收环形振荡器的一对振荡信号，并以预定的占空比产生输出信号。半加法器接收占空比缓冲器的输出信号，并且作为对占空比缓冲器的输出信号的异或运算的结果产生输出信号，并且作为对占空比的输出信号进行“与”运算的结果的输出信号缓冲区开关选择环形振荡器的振荡信号之一，输出信号作为异或运算的结果，输出信号作为AND运算的结果。通过使用频率合成器，可以选择高频环形振荡器的振荡频率输出信号之一，高频环路振荡器的振荡频率的两倍的输出信号以及与输入信号相同的频率的输出信号。

148. 发明申请

US20050093583A1 Fixed frequency clock output having a variable high frequency input clock and an unrelated fixed frequency reference signal 有权
标题翻译：具有可变高频输入时钟和不相关的固定频率参考信号的固定频率时钟输出
公开(公告)号：US20050093583A1
公开(公告)日：2005-05-05
申请号：US10696811
申请日：2003-10-30
申请人： Douglas Keithley , Richard Taylor , Mark Montierth
发明人： Douglas Keithley , Richard Taylor , Mark Montierth
IPC分类号： B41J2/44 , G06F1/04 , H03K5/22 , H03L7/16 , H04N1/405 , H03B21/00
CPC分类号： H03L7/16
摘要： A digital circuit generates very precise clock frequencies for applications that can tolerate a small degree of jitter but require exact long term frequencies, e.g. a video clock for a laser printer. Some subpixel jitter is acceptable, but the overall pixel rate remains exact and consistent. In some applications, the jitter may be desirable to smear the EMI spectrum. For example, if the high frequency input clock is modulated, the edges of the video clock will also be modulated yet remain within the jitter and frequency specification.
摘要翻译：数字电路为能够容忍小程度的抖动但需要精确的长期频率的应用产生非常精确的时钟频率，例如，用于激光打印机的视频时钟。一些子像素抖动是可接受的，但是整体像素速率保持精确和一致。在一些应用中，可能需要抖动以涂抹EMI频谱。例如，如果调制高频输入时钟，则视频时钟的边沿也将被调制，但仍保持在抖动和频率规范内。

149. 发明申请

US20050083137A1 Frequency synthesizer using a wide-band voltage controlled oscillator and a fast adaptive frequency calibration method 有权
标题翻译：使用宽带压控振荡器的频率合成器和快速自适应频率校准方法
公开(公告)号：US20050083137A1
公开(公告)日：2005-04-21
申请号：US10942119
申请日：2004-09-15
申请人： Han-il Lee , In-chul Hwang
发明人： Han-il Lee , In-chul Hwang
IPC分类号： H03L7/16 , H03L7/00 , H03L7/085 , H03L7/087 , H03L7/099 , H03L7/10 , H03L7/18
CPC分类号： H03L7/113 , H03L7/085 , H03L7/087 , H03L7/099 , H03L7/18
摘要： A frequency synthesizer is provided. The frequency synthesizer includes an adaptive frequency calibration circuit and a phase locked loop (PLL). The frequency synthesizer performs in a frequency lock mode and in a phase lock mode. In the frequency lock mode, the adaptive frequency calibration circuit compares the frequency of an input signal with the frequency of an output signal of a voltage controlled oscillator of the PLL and outputs control bits as a result of the comparison. The voltage controlled oscillator has a plurality of operating characteristic curves and selects a curve from among the plurality of operating characteristic curves in response to the control bits. In the phase lock mode, the PLL controls an output phase of the voltage controlled oscillator based on a tuning voltage from the selected operating characteristic curve.
摘要翻译：提供频率合成器。频率合成器包括自适应频率校准电路和锁相环（PLL）。频率合成器在频率锁定模式和相位锁定模式下执行。在频率锁定模式中，自适应频率校准电路将输入信号的频率与PLL的压控振荡器的输出信号的频率进行比较，并作为比较结果输出控制位。压控振荡器具有多个工作特性曲线，并响应于控制位选择多个操作特性曲线中的曲线。在锁相模式下，PLL根据所选工作特性曲线的调谐电压控制压控振荡器的输出相位。

150. 发明授权

US06876262B2 Technique for generating carrier frequencies with fast hopping capability 有权
标题翻译：用于产生具有快速跳变能力的载波频率的技术
公开(公告)号：US06876262B2
公开(公告)日：2005-04-05
申请号：US10626924
申请日：2003-07-25
申请人： Ranjit Gharpurey , Anuj Batra , Jaiganesh Balakrishnan , Anand G. Dabak
发明人： Ranjit Gharpurey , Anuj Batra , Jaiganesh Balakrishnan , Anand G. Dabak
IPC分类号： H03L7/00 , H03L7/16 , H03L7/18 , H04B1/40 , H04B1/69 , H04L27/00
CPC分类号： H04L27/0014 , H03L7/18 , H04B1/406 , H04B1/7136 , H04L2027/0016 , H04L2027/0053
摘要： A technique for generating carrier frequencies with fast hopping capability associated with multiband systems for ultra wideband applications. The technique employs a single VCO 20 that is locked in a PLL 30. The output of this VCO 20 is divided in the frequency domain. The divided frequencies thus obtained are combined in a single-sideband manner to obtain various other frequencies. The single-sideband combination requires open loop operations such as multiplication and addition or subtraction to implement, and hence is very fast. The VCO center frequency is not disturbed in the process. Since the required frequencies are generated in an open-loop fashion, instead of inside a PLL, the speed is increased by orders of magnitude.
摘要翻译：用于产生具有与用于超宽带应用的多频带系统相关联的具有快速跳变能力的载波频率的技术。该技术采用锁定在PLL 30中的单个VCO 20。该VCO 20的输出在频域中被划分。这样获得的划分频率以单边带方式组合以获得各种其它频率。单边带组合需要开环操作，例如乘法和加法或减法来实现，因此非常快。 VCO中心频率在此过程中不受干扰。由于所需的频率是以开环方式产生的，而不是在PLL内部，速度增加了数量级。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式