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141. 发明申请

US20040054949A1 Direct slave addressing to indirect slave addressing 失效
标题翻译：直接从站寻址到间接从站寻址
公开(公告)号：US20040054949A1
公开(公告)日：2004-03-18
申请号：US10276486
申请日：2003-09-08
发明人： Nevil Morley Hunt , Malcolm Philip Ross
IPC分类号： G01R031/28
CPC分类号： G06F13/4217
摘要： A computer bus system comprises: a direct address bus; at least one bus master device and at least one bus slave device, the bus master device and bus slave device being connected to the bus so that the bus master device may communicate with the bus slave device over the bus. The bus has an address space assigned to different devices connected to the bus and is a multiplexed address/data bus for transferring blocks of data (63,76) in a direct address transaction (60) between the devices. Each direct address transaction (60) comprises a burst transaction (61) having an address phase (12,62) with a bus space address value (62) followed by a data phase (63). The bus slave device includes an indirect address device addressable in an indirect address transaction (70) that has an address register load transaction (71) followed by a data register load transaction (72). The indirect address device has a memory with memory locations identified by address values loaded into the address register of the indirect address device. The slave device includes a transaction translation device between the bus and the indirect address device that translates the direct address transaction (61) to an indirect address transaction (70) including mapping (64) the bus space address value (62) to the destination address value (74). Therefore, a direct address transaction (60) received by the slave device for communicated blocks of data is presented to the indirect address device as an indirect address transaction (70).
摘要翻译：计算机总线系统包括：直接地址总线; 至少一个总线主设备和至少一个总线从设备，总线主设备和总线从设备连接到总线，使得总线主设备可以通过总线与总线从设备通信。总线具有分配给连接到总线的不同设备的地址空间，并且是用于在设备之间的直接地址事务（60）中传送数据块（63,76）的复用地址/数据总线。每个直接地址事务（60）包括具有地址相位（12,62）的突发交易（61），其具有总线空间地址值（62），后跟数据相位（63）。总线从设备包括可以在具有地址寄存器加载事务（71）后跟数据寄存器加载事务（72）的间接寻址事务（70）中寻址的间接地址设备。间接地址设备具有存储器，其存储器位置由加载到间接地址设备的地址寄存器中的地址值标识。从设备包括在总线和间接地址设备之间的事务转换设备，其将直接地址事务（61）转换为间接地址事务（70），包括将总线空间地址值（64）映射（64）到目的地地址价值（74）。因此，由从设备接收的所传送的数据块的直接地址事务（60）作为间接地址事务被提供给间接地址设备（70）。

142. 发明授权

US06694400B1 PCI system controller capable of delayed transaction 有权
标题翻译： PCI系统控制器能够延迟交易
公开(公告)号：US06694400B1
公开(公告)日：2004-02-17
申请号：US09451121
申请日：1999-11-30
申请人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Sheng-Chang Peng , Tse-Hsien Wang
发明人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Sheng-Chang Peng , Tse-Hsien Wang
IPC分类号： G06F1338
CPC分类号： G06F13/4217
摘要： A method of conducting delayed data transaction on a PCI system and its associated devices. The delayed data transaction is carried out using a PCI system to transmit data between an initiator and a responder. Both the initiator and the responder are coupled to a PCI bus. The delayed transaction in the PCI system includes a number of steps. To begin with, the initiator will send out a request to use the PCI bus so that data transmission can be conducted with respect to the responder. If the responder accepts the request but unable to secure the requested data soon enough, the responder will generate a defer identifier that corresponds to the requesting initiator. Next, a stop signal and the defer identifier generated by the responder will be returned to the initiator, indicating that the request has been accepted. When the requested data is ready in the responder, the responder will forward the defer identifier again. The initiator picks up the defer identifier and prepares according to the buffer identifier in it. Then, data transmission between the initiator and the responder begins.
摘要翻译：在PCI系统及其相关设备上进行延迟数据交易的方法。延迟数据事务使用PCI系统在启动器和应答器之间传输数据。启动器和应答器都与PCI总线相连。 PCI系统中的延迟事务包括多个步骤。首先，启动器将发出使用PCI总线的请求，以便可以对响应者进行数据传输。如果响应者接受请求但不能足够快地保护所请求的数据，则响应者将生成对应于请求的发起者的延迟标识符。接下来，由响应者生成的停止信号和延迟标识符将被返回给启动器，指示该请求已被接受。当请求的数据在响应者中准备就绪时，响应者将再次转发延迟标识符。发起人拿起延迟标识符，并根据缓冲区标识符进行准备。然后，启动器和应答器之间的数据传输开始。

143. 发明申请

US20030218484A1 Device and method for synchronizing an exchange of data with a remote member 有权
标题翻译：用于与远程成员同步数据交换的设备和方法
公开(公告)号：US20030218484A1
公开(公告)日：2003-11-27
申请号：US10405958
申请日：2003-04-02
申请人： STMICROELECTRONICS S.A.
发明人： Nicolas Graciannette , Benoit Marchand
IPC分类号： H03L007/06
CPC分类号： G06F13/4217
摘要： A device is provided for synchronizing, on a reference clock signal, an exchange of data with a remote member. The device includes a main variable delay line controlled by a first processing unit coupled to a phase comparator in order to generate a delayed clock signal transmitted to the remote member. One input of the main variable delay line receives the reference clock signal. The device also includes a first terminal for receiving a clock signal image received by the remote member, a first auxiliary variable delay line having one input connected to the first terminal and one output connected to a first input of the phase comparator, a second auxiliary variable delay line having one input connected to the input of the main variable delay line and one output connected to a second input of the phase comparator, and a second processing unit controlling the first and second auxiliary variable delay lines so that the signal image received by the remote member is offset with respect to the reference clock signal, by a phase suitable for synchronizing the exchange of data on the reference clock signal.
摘要翻译：提供了一种设备，用于在参考时钟信号上与远程成员进行数据交换。该装置包括由连接到相位比较器的第一处理单元控制的主可变延迟线，以便产生发送给远程成员的延迟时钟信号。主可变延迟线的一个输入端接收参考时钟信号。该装置还包括用于接收由远程成员接收的时钟信号图像的第一终端，具有连接到第一终端的一个输入和连接到相位比较器的第一输入的一个输出的第一辅助可变延迟线，第二辅助变量延迟线，其一个输入连接到主可变延迟线的输入，一个输出连接到相位比较器的第二输入，第二处理单元控制第一和第二辅助可变延迟线，使得由远程成员相对于参考时钟信号偏移适合于同步参考时钟信号上的数据交换的相位。

144. 发明授权

US06646953B1 Single-clock, strobeless signaling system 失效
标题翻译：单时钟，无频闪信号系统
公开(公告)号：US06646953B1
公开(公告)日：2003-11-11
申请号：US09611936
申请日：2000-07-06
申请人： Donald C. Stark
发明人： Donald C. Stark
IPC分类号： G11C800
CPC分类号： G11C7/222 , G06F13/4217 , G11C7/1072 , G11C7/22
摘要： A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path.
摘要翻译：信令系统包括信令路径，耦合到信令路径的主设备，耦合到信令路径的从设备和时钟发生器。从设备包括定时电路，用于产生具有相对于由时钟发生器提供的时钟信号的相位偏移的内部时钟信号，相位偏移至少部分地由信号路径上的信号传播时间确定。

145. 发明授权

US06625743B1 Method for synchronizing generation and consumption of isochronous data 有权
标题翻译：同步数据同步生成和消耗的方法
公开(公告)号：US06625743B1
公开(公告)日：2003-09-23
申请号：US09933290
申请日：2001-08-20
申请人： Dale E. Gulick
发明人： Dale E. Gulick
IPC分类号： G06F112
CPC分类号： G06F1/12 , G06F13/4217
摘要： A method of synchronizing the generation and consumption of isochronous data in a computer system. In one embodiment, a computer system implements a method comprising providing a plurality of clocks to a plurality of isochronous sinks or sources configured to generate or consume the isochronous data, outputting a master clock signal to the plurality of isochronous sinks or sources, synchronizing said clocks to said master clock signal so that the generation or consumption of the isochronous data is synchronized to said master clock signal, outputting said master clock signal to an interrupt controller, and generating an interrupt based on said master clock signal, wherein a processor schedules one or more tasks that generate or consume data based on said interrupt. The isochronous sinks or sources may also be synched to a multiple of the master clock signal.
摘要翻译：一种在计算机系统中同步同步数据的生成和消耗的方法。在一个实施例中，计算机系统实现一种方法，包括向被配置为产生或消耗同步数据的多个同步宿或源提供多个时钟，将主时钟信号输出到多个同步宿或源，同步所述时钟到所述主时钟信号，使得同步数据的产生或消耗与所述主时钟信号同步，将所述主时钟信号输出到中断控制器，并且基于所述主时钟信号产生中断，其中处理器调度一个或基于所述中断产生或消耗数据的更多任务。同步吸收器或源也可以被同步到主时钟信号的倍数。

146. 发明申请

US20030163615A1 Peripheral or memory device having a combined ISA bus and LPC bus 失效
标题翻译：具有组合ISA总线和LPC总线的外设或存储器件
公开(公告)号：US20030163615A1
公开(公告)日：2003-08-28
申请号：US10081249
申请日：2002-02-22
发明人： Kuo-Hwa Yu
IPC分类号： G06F013/00
CPC分类号： G06F13/4217
摘要： A peripheral or memory device has a bus, a first bus decoder circuit coupled to the bus for decoding a first type of bus signal, and a second bus decoder circuit coupled to the bus for decoding a second type of bus signal. The device also includes a circuit for detecting whether the bus is a first type of bus or a second type of bus, and outputting a select or detect signal to a switch. The switch is coupled to the first bus decoder circuit for providing a first bus enable signal thereto, and the switch is coupled to the second bus decoder circuit for providing a second bus enable signal thereto, depending on the nature of the select or detect signal.
摘要翻译：外围设备或存储设备具有总线，耦合到总线的第一总线解码器电路，用于对第一类型的总线信号进行解码，以及耦合到总线的第二总线解码器电路，用于对第二类型的总线信号进行解码。该装置还包括用于检测总线是第一类型总线还是第二类型总线的电路，并向开关输出选择或检测信号。该开关耦合到第一总线解码器电路，用于向其提供第一总线使能信号，并且该开关耦合到第二总线解码器电路，用于根据选择或检测信号的性质向其提供第二总线使能信号。

147. 发明授权

US06601121B2 Quad pumped bus architecture and protocol 失效
公开(公告)号：US06601121B2
公开(公告)日：2003-07-29
申请号：US09925692
申请日：2001-08-10
申请人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
发明人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.

148. 发明授权

US06467009B1 Configurable processor system unit 有权
标题翻译：可配置的处理器系统单元
公开(公告)号：US06467009B1
公开(公告)日：2002-10-15
申请号：US09172918
申请日：1998-10-14
申请人： Steven Paul Winegarden , Bart Reynolds , Brian Fox , Jean-Didier Allegrucci , Sridhar Krishnamurthy , Danesh Tavana , Arye Ziklik , Andreas Papaliolios , Stanley S. Yang , Fung Fung Lee
发明人： Steven Paul Winegarden , Bart Reynolds , Brian Fox , Jean-Didier Allegrucci , Sridhar Krishnamurthy , Danesh Tavana , Arye Ziklik , Andreas Papaliolios , Stanley S. Yang , Fung Fung Lee
IPC分类号： G06F100
CPC分类号： G06F15/7867 , G06F13/4217
摘要： The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.
摘要翻译：可配置处理器系统包括处理器，内部系统总线和经由内部系统总线在单个集成电路上互连的可编程逻辑。

149. 发明申请

US20020138657A1 Data transfer circuit and data transfer method 审中-公开
标题翻译：数据传输电路和数据传输方式
公开(公告)号：US20020138657A1
公开(公告)日：2002-09-26
申请号：US10104411
申请日：2002-03-22
申请人： Ando Electric Co., Ltd.
发明人： Masayuki Hirofuji
IPC分类号： G06F015/16
CPC分类号： G06F13/4217
摘要： A data transfer circuit and a data transfer method are provided that can minimize the time required for transferring identical data to a plurality of data registers. A data transfer circuit for writing parallel data transferred through a data bus into a plurality of data registers is provided with auxiliary registers which respectively correspond to the data registers, a write timing determining section, and an auxiliary register setting section. At a first timing, the auxiliary register setting section makes the auxiliary registers store the respective bit values of parallel data transferred through the data bus. At a second timing, after the first timing, the write timing determining section makes the data registers store another parallel data transferred through the data bus in accordance with the respective bit values stored in the auxiliary registers.
摘要翻译：提供了一种数据传输电路和数据传输方法，其可将将相同数据传送到多个数据寄存器所需的时间最小化。用于将通过数据总线传送的并行数据写入多个数据寄存器的数据传送电路设置有分别对应于数据寄存器，写时序确定部分和辅助寄存器设置部分的辅助寄存器。在第一定时，辅助寄存器设置部分使辅助寄存器存储通过数据总线传送的并行数据的各个位值。在第二定时，在第一定时之后，写时序确定部分使得数据寄存器根据存储在辅助寄存器中的相应位值存储通过数据总线传送的另一个并行数据。

150. 发明授权

US06442628B1 Method and system for automatically determining maximum data throughput over a bus 有权
标题翻译：用于自动确定总线上最大数据吞吐量的方法和系统
公开(公告)号：US06442628B1
公开(公告)日：2002-08-27
申请号：US09300818
申请日：1999-04-27
申请人： Vincent J. Bastiani , Lawrence J. Lamers
发明人： Vincent J. Bastiani , Lawrence J. Lamers
IPC分类号： G06F300
CPC分类号： G06F13/4217
摘要： A method and system are provided for determining maximum data throughput between a host adapter and one or more target devices coupled to the host adapter through a bus. A first set of device identifying data is obtained from a target device over the bus. Then, a maximum data throughput rate is negotiated between the host adapter and the target device over the bus. Next, a second set of device identifying data is obtained from the target device over the bus at the negotiated maximum data throughput rate. Read and write tests are performed to determine the maximum data throughput rate. When the first and second sets of device identifying data are identical, the host adapter and the target device are operated over the bus at the negotiated maximum data throughput rate.
摘要翻译：提供了一种方法和系统，用于确定主机适配器与通过总线耦合到主机适配器的一个或多个目标设备之间的最大数据吞吐量。通过总线从目标设备获得第一组设备标识数据。然后，通过总线在主机适配器和目标设备之间协商最大数据吞吐率。接下来，通过总线上以协商的最大数据吞吐速率从目标设备获得第二组设备标识数据。执行读写测试以确定最大数据吞吐率。当第一和第二组设备标识数据相同时，主机适配器和目标设备以协商的最大数据吞吐速率通过总线进行操作。

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