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141. 发明授权

US07388420B2 Rewriteable electronic fuses 有权
标题翻译：可重写电子保险丝
公开(公告)号：US07388420B2
公开(公告)日：2008-06-17
申请号：US10814866
申请日：2004-03-30
申请人： Christopher J. Diorio , Frédéric J. Bernard , Todd E. Humes , Alberto Pesavento
发明人： Christopher J. Diorio , Frédéric J. Bernard , Todd E. Humes , Alberto Pesavento
IPC分类号： H01H37/76
CPC分类号： G11C16/0441 , G11C7/20 , G11C14/00 , G11C16/045
摘要： Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predetermined states as power-up or reset signals are applied to the fuses. Although not required, the nonvolatile memory elements used in the rewriteable electronic fuses may comprise floating-gate transistors. An amount of charge stored on the floating gate of a given floating-gate transistor determines the memory value and, consequently, the state to which a fuse settles upon power-up or reset of the fuse.
摘要翻译：可重写电子熔丝包括耦合到一个或多个非易失性存储元件的锁存器和/或逻辑门。非易失性存储器元件被配置为被编程为能够使相关联的电子电路稳定到预定状态的存储器值，因为上电或复位信号被施加到保险丝。虽然不是必需的，但是在可重写电子熔丝中使用的非易失性存储元件可以包括浮栅晶体管。存储在给定浮栅晶体管的浮置栅极上的电荷量确定存储器值，并且因此确定保险丝上电或复位时保险丝熔断的状态。

142. 发明授权

US07375398B2 High voltage FET gate structure 有权
标题翻译：高压FET栅极结构
公开(公告)号：US07375398B2
公开(公告)日：2008-05-20
申请号：US11138888
申请日：2005-05-26
申请人： Bin Wang , Chih-Hsin Wang
发明人： Bin Wang , Chih-Hsin Wang
IPC分类号： H01L23/62
CPC分类号： H01L29/4983 , H01L29/0653 , H01L29/4916 , H01L29/7833 , H01L29/7835 , H01L29/7836
摘要： A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second well defines a first surface region to receive a drain contact. A third well is located at least partially in the first well, includes doped implants of the second type, and is adapted to receive a source contact. As such, the third well defines a channel between itself and the second well within the first well. A gate is disposed over the channel. At least a first portion of the gate is disposed over the p-n junction, and includes doped implants of the first type. A number of permutations are allowed for doping the remainder of the gate.
摘要翻译：用于在高电压下操作的FET器件包括分别掺杂有第一类型和第二类型的植入物的衬底，衬底内的第一阱和第二阱。第一和第二阱限定p-n结。第二阱内的场氧化物层限定了接收漏极接触的第一表面区域。第三阱至少部分地位于第一阱中，包括第二类型的掺杂植入物，并且适于接收源极接触。这样，第三井在第一井内定义了自身与第二井之间的通道。通道上设置一个门。栅极的至少第一部分设置在p-n结上方，并且包括第一类型的掺杂植入物。许多排列允许掺杂栅极的其余部分。

143. 发明申请

US20080056010A1 Non-volatile memory with programming through band-to-band tunneling and impact ionization gate current 有权
标题翻译：非易失性存储器，通过带 - 带隧穿和冲击电离栅极电流进行编程
公开(公告)号：US20080056010A1
公开(公告)日：2008-03-06
申请号：US11601474
申请日：2006-11-16
申请人： Andrew E. Horch
发明人： Andrew E. Horch
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/12
摘要： Electronic circuitry is described having a first transistor having a first gate dielectric located between an electrically floating gate and a semiconductor substrate. The first injection current flows through the first gate dielectric to establish a first amount of electrical charge on the gate electrode. The electronic circuitry also includes a second transistor having a second gate dielectric located between the gate electrode and the semiconductor substrate. A band-to-band tunneling current flows between valence and conduction bands of the second transistor to create a second injection current that flows through the second gate dielectric to establish the first amount of electrical charge on the gate electrode. Non volatile memory cell circuits having the above described circuitry are also described.
摘要翻译：电子电路被描述为具有位于电浮置栅极和半导体衬底之间的第一栅极电介质的第一晶体管。第一注入电流流过第一栅极电介质以在栅电极上建立第一量的电荷。电子电路还包括具有位于栅电极和半导体衬底之间的第二栅极电介质的第二晶体管。带间隧穿电流在第二晶体管的价带和导带之间流动，以产生流过第二栅极电介质的第二注入电流，以在栅电极上建立第一量的电荷。还描述了具有上述电路的非易失性存储单元电路。

144. 外观设计

USD562810S1 Radio frequency identification tag antenna assembly 有权
公开(公告)号：USD562810S1
公开(公告)日：2008-02-26
申请号：US29285827
申请日：2007-04-11
申请人： Ronald A. Oliver
设计人： Ronald A. Oliver

145. 发明申请

US20080006702A2 RFID SYSTEM COMPONENTS IMPLEMENTING ADJUSTED BACKSCATTER CALCULATIONS AND METHODS 有权
标题翻译： RFID系统组件实施调整后的计算机和方法
公开(公告)号：US20080006702A2
公开(公告)日：2008-01-10
申请号：US11114614
申请日：2005-04-25
申请人： Christopher Diorio , Kurt Sundstrom , Scott Cooper , Todd Humes
发明人： Christopher Diorio , Kurt Sundstrom , Scott Cooper , Todd Humes
IPC分类号： G06K19/06
CPC分类号： G06K19/0723 , G06K7/0008 , H03J1/0058
摘要： RFID system components, such as readers and tags, communicate by a reader transmitting waveforms that encode a calibration symbol and a divide ratio. Tags include a processor to determine a backscatter link period result by dividing a count value representing the calibration symbol by the divide ratio and adding an adjustment. Tags modulate a backscatter waveform that includes symbols using a link period determined from the result.
摘要翻译：诸如读取器和标签的RFID系统组件由读取器传送，该读取器发送编码校准符号和分频比的波形。标签包括通过将表示校准符号的计数值除以除法比率并且添加调整来确定反向散射链路周期结果的处理器。标签使用从结果确定的链路周期调制包括符号的反向散射波形。

146. 发明授权

US07283390B2 Hybrid non-volatile memory 有权
标题翻译：混合非易失性存储器
公开(公告)号：US07283390B2
公开(公告)日：2007-10-16
申请号：US11237099
申请日：2005-09-28
申请人： Alberto Pesavento
发明人： Alberto Pesavento
IPC分类号： G11C11/34
CPC分类号： G11C16/3468 , G11C11/005 , G11C16/0416 , G11C16/0441 , G11C16/3477 , G11C16/3486 , G11C2216/10 , G11C2216/26
摘要： A non-volatile memory (NVM) circuit includes at least two types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provide an output upon transitioning to a power-on state, NVM circuits that provide an ON/OFF state output, and the like. Some of the outputs are used to calibrate circuits within a device following power-on. Other outputs are used to store information to be employed by various circuits.
摘要翻译：非易失性存储器（NVM）电路包括共享公共支持电路的至少两种类型的NVM子电路。不同类型的NVM子电路包括在寻址时提供逻辑输出的普通NVM电路，在转换到通电状态时提供输出的可编程熔丝，提供ON / OFF状态输出的NVM电路等。一些输出用于在上电之后校准器件内的电路。其他输出用于存储由各种电路采用的信息。

147. 发明申请

US20070236335A1 Ahead-of-time scheduling of commands in RFID reader systems 有权
标题翻译： RFID阅读器系统中的命令的时间调度
公开(公告)号：US20070236335A1
公开(公告)日：2007-10-11
申请号：US11509290
申请日：2006-08-23
申请人： Ali Aiouaz , David Ord , Omar Khwaja
发明人： Ali Aiouaz , David Ord , Omar Khwaja
IPC分类号： H04Q5/22
CPC分类号： G06K7/10297 , H04L1/16
摘要： RFID reader systems, software and methods precompute one or more reader commands, before a tag actually responds to an earlier transmitted command. This way a system can result at a high data rate, while meeting specification requirements of responding within a preset time.
摘要翻译： RFID标签系统，软件和方法在一个标签实际响应早期传输的命令之前预先计算一个或多个读取器命令。这样一来，系统就可以达到高的数据速率，同时满足在预设时间内响应的规范要求。

148. 发明授权

US07242614B2 Rewriteable electronic fuses 有权
公开(公告)号：US07242614B2
公开(公告)日：2007-07-10
申请号：US10813907
申请日：2004-03-30
申请人： Christopher J. Diorio , Frédéric J. Bernard , Todd E. Humes , Alberto Pesavento
发明人： Christopher J. Diorio , Frédéric J. Bernard , Todd E. Humes , Alberto Pesavento
IPC分类号： G11C11/34 , G11C17/18
CPC分类号： G11C16/0441 , G11C14/00 , G11C16/045 , H01L27/105 , H01L27/115 , H01L29/7883 , H03K3/02335
摘要： Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predetermined states as power-up or reset signals are applied to the fuses. Although not required, the nonvolatile memory elements used in the rewriteable electronic fuses may comprise floating-gate transistors. An amount of charge stored on the floating gate of a given floating-gate transistor determines the memory value and, consequently, the state to which a fuse settles upon power-up or reset of the fuse.

149. 发明申请

US20070136585A1 Determining authentication of RFID tags for indicating legitimacy of their associated items 审中-公开
标题翻译：确定用于指示其相关项目合法性的RFID标签的认证
公开(公告)号：US20070136585A1
公开(公告)日：2007-06-14
申请号：US11637479
申请日：2006-12-11
申请人： Christopher Diorio , Gregory Kavounas
发明人： Christopher Diorio , Gregory Kavounas
IPC分类号： H04L9/00
CPC分类号： G06F21/35 , G06Q30/06
摘要： RFID readers, computers, and methods are provided for determining the authentication of one or more RFID tags associated with a proffered item. In some embodiments, an Item Identifier (II) is input from the tags, along with a Declared Password (DP) corresponding to the II. A question is generated about whether the DP is regarded as proper for the II by a reference database, and applied to data of the reference database. A host of the database uses special permissions, such that an answer to the question does not reveal the good password, unless the DP is already the right one. Beyond the authentication of the tag, the answer can further indicate the legitimacy of the proffered item, such as for a supply chain or at a Customs Office.
摘要翻译： RFID读取器，计算机和方法被提供用于确定与提供的项目相关联的一个或多个RFID标签的认证。在一些实施例中，从标签输入项目标识符（II）以及对应于II的声明密码（DP）。产生关于DP被参考数据库视为是否适合II并且应用于参考数据库的数据的问题。数据库的主机使用特殊权限，这样一来，问题的答案就不会显示出良好的密码，除非DP已经是正确的密码了。除了标签的认证之外，答案可以进一步表明所提供项目的合法性，例如供应链或海关。

150. 发明申请

US20070019477A1 Method and apparatus for programming single-poly pFET-based nonvolatile memory cells 有权
公开(公告)号：US20070019477A1
公开(公告)日：2007-01-25
申请号：US11528262
申请日：2006-09-26
申请人： Christopher Diorio , Todd Humes
发明人： Christopher Diorio , Todd Humes
IPC分类号： G11C11/34
CPC分类号： G11C16/3468 , G11C16/3404 , G11C16/3472 , G11C16/3477
摘要： Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are injected onto a floating gate of the cell. Following a predetermined event, the single-poly pFET is biased to induce impact-ionized hot-electron injection (IHEI). The predetermined event may be, for example, the expiration of a predetermined time period or a determination that a channel has been formed by the BTBT injection process that is sufficiently conducting to support IHEI. Employing BTBT permits a previously overerased or stuck bit to be “unstuck” or “removed” and thus be made usable (i.e., able to be programmed) again.

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