专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

141. 发明申请

US20140061724A1 High Electron Mobility Transistor and Manufacturing Method Thereof 有权
标题翻译：高电子迁移率晶体管及其制造方法
公开(公告)号：US20140061724A1
公开(公告)日：2014-03-06
申请号：US13597599
申请日：2012-08-29
申请人： Chih-Fang Huang , Chien-Wei Chiu , Ting-Fu Chang , Tsung-Yu Yang , Tsung-Yi Huang
发明人： Chih-Fang Huang , Chien-Wei Chiu , Ting-Fu Chang , Tsung-Yu Yang , Tsung-Yi Huang
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/41766 , H01L29/7787
摘要： The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.
摘要翻译：本发明公开了一种高电子迁移率晶体管（HEMT）及其制造方法。 HEMT包括半导体层，半导体层上的势垒层，阻挡层上的压电层，压电层上的栅极，栅极两侧的源极和漏极，其中半导体的每个带隙层，阻挡层和压电层部分但不完全与其它两个带隙重叠。栅极形成为用于接收栅极电压。二维电子气体（2DEG）形成在半导体层和阻挡层之间的结的一部分中，但不在压电层的至少一部分下方，其中2DEG电连接到源极和漏极。

142. 发明授权

US08653594B2 Double diffused metal oxide semiconductor device and manufacturing method thereof 有权
公开(公告)号：US08653594B2
公开(公告)日：2014-02-18
申请号：US13066622
申请日：2011-04-20
申请人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
发明人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L29/66
CPC分类号： H01L29/4238 , H01L21/28114 , H01L21/823425 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/086 , H01L29/0865 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

143. 发明申请

US20130341719A1 Hybrid High Voltage Device and Manufacturing Method Thereof 有权
标题翻译：混合高压器件及其制造方法
公开(公告)号：US20130341719A1
公开(公告)日：2013-12-26
申请号：US13529963
申请日：2012-06-21
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7817 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/402 , H01L29/42368 , H01L29/4238 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.
摘要翻译：本发明公开了一种混合式高压装置及其制造方法。混合高压器件形成在第一导电型衬底中，并且包括至少一个横向双扩散金属氧化物半导体（LDMOS）器件区域和至少一个通气器件区域，其中LDMOS器件区域和通气器件区域被连接在宽度方向上以交替的顺序布置。此外，LDMOS器件区域和通风装置区域的相应的高压井，源极，漏极，体区和栅极分别彼此连接。

144. 发明申请

US20130313641A1 DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE 有权
标题翻译：双重扩散金属氧化物半导体器件
公开(公告)号：US20130313641A1
公开(公告)日：2013-11-28
申请号：US13480360
申请日：2012-05-24
申请人： Tsung-Yi Huang , Chien-Wei Chiu , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Wei Chiu , Chien-Hao Huang
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/66681
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device. The DMOS device is formed in a substrate, and includes a high voltage well, a first field oxide region, a first gate, a first source, a drain, a body region, a body electrode, a second field oxide region, a second gate, and a second source. The second field oxide region and the first field oxide region are separated by the high voltage well and the body region. A part of the second gate is on the second field oxide region, and another part of the second gate is on the body region. The second gate is electrically connected to the first gate, and the second source is electrically connected to the first source, such that when the DMOS device is ON, a surface channel and a buried channel are formed.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）装置。 DMOS器件形成在衬底中，并且包括高电压阱，第一场氧化物区域，第一栅极，第一源极，漏极，体区域，体电极，第二场氧化物区域，第二栅极，和第二个来源。第二场氧化物区域和第一场氧化物区域被高电压井和身体区域分开。第二栅极的一部分在第二场氧化物区域上，第二栅极的另一部分位于主体区域上。第二栅极电连接到第一栅极，并且第二源极电连接到第一源极，使得当DMOS器件导通时，形成表面沟道和埋入沟道。

145. 发明申请

US20130270571A1 SCHOTTKY BARRIER DIODE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：肖特彼勒二极管及其制造方法
公开(公告)号：US20130270571A1
公开(公告)日：2013-10-17
申请号：US13448163
申请日：2012-04-16
申请人： Chih-Fang Huang , Tsung-Yu Yang , Ting-Fu Chang , Tsung-Yi Huang , Chien-Wei Chiu
发明人： Chih-Fang Huang , Tsung-Yu Yang , Ting-Fu Chang , Tsung-Yi Huang , Chien-Wei Chiu
IPC分类号： H01L29/20 , H01L21/20
CPC分类号： H01L29/475 , H01L29/0692 , H01L29/2003 , H01L29/205 , H01L29/452 , H01L29/66212 , H01L29/872
摘要： The present invention discloses a Schottky barrier diode (SBD) and a manufacturing method thereof. The SBD is formed on a substrate. The SBD includes: a gallium nitride (GaN) layer; an aluminum gallium nitride (AlGaN), formed on the GaN layer; a high work function conductive layer, formed on the AlGaN layer, wherein a first Schottky contact is formed between the high work function conductive layer and the AlGaN layer; a low work function conductive layer, formed on the AlGaN layer, wherein a second Schottky contact is formed between the low work function conductive layer and the AlGaN layer; and an ohmic contact metal layer, formed on the AlGaN layer, wherein an ohmic contact is formed between the ohmic contact metal layer and the AlGaN layer, and wherein the ohmic contact conductive layer is separated from the high and low work function conductive layers by a dielectric layer.
摘要翻译：本发明公开了一种肖特基势垒二极管（SBD）及其制造方法。 SBD形成在基板上。 SBD包括：氮化镓（GaN）层; 在GaN层上形成的氮化镓铝（AlGaN）; 形成在所述AlGaN层上的高功函导电层，其中在所述高功函导电层和所述AlGaN层之间形成第一肖特基接触; 形成在AlGaN层上的低功函数导电层，其中在低功函导电层和AlGaN层之间形成第二肖特基接触; 以及形成在AlGaN层上的欧姆接触金属层，其中在欧姆接触金属层和AlGaN层之间形成欧姆接触，并且其中欧姆接触导电层与高和低功函导电层分开一个电介质层。

146. 发明申请

US20130217196A1 High Voltage Device and Manufacturing Method Thereof 有权
标题翻译：高压器件及其制造方法
公开(公告)号：US20130217196A1
公开(公告)日：2013-08-22
申请号：US13844926
申请日：2013-03-16
申请人： Tsung-Yi Huang , Huan-Ping Chu
发明人： Tsung-Yi Huang , Huan-Ping Chu
IPC分类号： H01L29/66
CPC分类号： H01L29/0878 , H01L29/0847 , H01L29/1083 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate has an upper surface. The high voltage device includes: a second conductive type buried layer, which is formed in the substrate; a first conductive type well, which is formed between the upper surface and the buried layer; and a second conductive type well, which is connected to the first conductive type well and located at different horizontal positions. The second conductive type well includes a well lower surface, which has a first part and a second part, wherein the first part is directly above the buried layer and electrically coupled to the buried layer; and the second part is not located above the buried layer and forms a PN junction with the substrate.
摘要翻译：本发明公开了一种高压器件及其制造方法。高压器件形成在第一导电型衬底中，其中衬底具有上表面。高压器件包括：形成在衬底中的第二导电型掩埋层; 第一导电型阱，其形成在上表面和埋层之间; 以及第二导电型阱，其连接到第一导电类型阱并且位于不同的水平位置。第二导电类型阱包括井下表面，其具有第一部分和第二部分，其中第一部分直接在掩埋层的上方并电耦合到掩埋层; 并且第二部分不位于掩埋层的上方并与衬底形成PN结。

147. 发明授权

US08501567B2 Manufacturing method of high voltage device 有权
公开(公告)号：US08501567B2
公开(公告)日：2013-08-06
申请号：US13317568
申请日：2011-10-21
申请人： Tsung-Yi Huang , Yuh-Chyuan Wang
发明人： Tsung-Yi Huang , Yuh-Chyuan Wang
IPC分类号： H01L21/8234
CPC分类号： H01L29/66659 , H01L21/266 , H01L21/82385 , H01L21/823857 , H01L27/0922 , H01L29/0847 , H01L29/1083 , H01L29/7835
摘要： The present invention discloses a manufacturing method of a high voltage device. The high voltage device is formed in a first conductive type substrate. The high-voltage device includes: a second conductive type buried layer; a first conductive type high voltage well; and a second conductive type body. The high voltage well is formed by the same step for forming a first conductive type well or a first conductive type channel stop layer of a low voltage device formed in the same substrate. The body is formed by the same step for forming a second conductive type well of the low voltage device.

148. 发明申请

US20130181319A1 Trench Schottky Barrier Diode and Manufacturing Method Thereof 失效
标题翻译：沟槽肖特基势垒二极管及其制造方法
公开(公告)号：US20130181319A1
公开(公告)日：2013-07-18
申请号：US13543844
申请日：2012-07-08
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/872 , H01L29/0615 , H01L29/402 , H01L29/66143 , H01L29/8725
摘要： The present invention discloses a trench Schottky barrier diode (SBD) and a manufacturing method thereof. The trench SBD includes: an epitaxial layer, formed on a substrate; multiple mesas, defined by multiple trenches; a field plate, formed on the epitaxial layer and filled in the multiple trenches, wherein a Schottky contact is formed between the field plate and top surfaces of the mesas; a termination region, formed outside the multiple mesas and electrically connected to the field plate; a field isolation layer, formed on the upper surface and located outside the termination region; and at least one mitigation electrode, formed below the upper surface outside the termination region, and is electrically connected to the field plate through the field isolation layer, wherein the mitigation electrode and the termination region are separated by part of a dielectric layer and part of the epitaxial layer.
摘要翻译：本发明公开了一种沟槽肖特基势垒二极管（SBD）及其制造方法。沟槽SBD包括：形成在衬底上的外延层; 由多个沟槽限定的多个台面; 场板，形成在所述外延层上并填充在所述多个沟槽中，其中在所述场板和所述台面的顶表面之间形成肖特基接触; 终端区域，形成在多个台面之外并电连接到场板; 场隔离层，形成在上表面并位于端接区域外部; 以及形成在终端区域外的上表面下方的至少一个缓解电极，并且通过场隔离层电连接到场板，其中缓解电极和端接区域被介电层的一部分分隔开，外延层。

149. 发明申请

US20130093011A1 High Voltage Device and Manufacturing Method Thereof 审中-公开
标题翻译：高压器件及其制造方法
公开(公告)号：US20130093011A1
公开(公告)日：2013-04-18
申请号：US13276111
申请日：2011-10-18
申请人： Tsung-Yi Huang , Chien-Wei Chiu
发明人： Tsung-Yi Huang , Chien-Wei Chiu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66681 , H01L29/0623 , H01L29/1083 , H01L29/66659 , H01L29/7813 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a substrate. The high voltage device includes: a gate, a source and drain, a drift region, and a mitigation region. The gate is formed on an upper surface of the substrate. The source and drain are located at both sides of the gate below the upper surface respectively, and the source and drain are separated by the gate. The drift region is located at least between the gate and the drain. The mitigation region is formed below the drift region, and the drift region has an edge closer to the source. A vertical distance between this edge of the drift region and the mitigation region is less than or equal to five times of a depth of the drift region.
摘要翻译：本发明公开了一种高压器件及其制造方法。高压器件形成在衬底中。高电压装置包括：栅极，源极和漏极，漂移区和缓解区。栅极形成在衬底的上表面上。源极和漏极分别位于栅极下方的两侧，源极和漏极由栅极分开。漂移区域至少位于栅极和漏极之间。缓冲区形成在漂移区下方，漂移区具有靠近源的边。漂移区域的这个边缘与缓解区域之间的垂直距离小于或等于漂移区域的深度的五倍。

150. 发明授权

US08129783B2 Lateral power MOSFET with high breakdown voltage and low on-resistance 有权
标题翻译：具有高击穿电压和低导通电阻的侧向功率MOSFET
公开(公告)号：US08129783B2
公开(公告)日：2012-03-06
申请号：US12329285
申请日：2008-12-05
申请人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu
发明人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0634 , H01L29/0878 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region.
摘要翻译：提供具有高击穿电压和低导通电阻的半导体器件。一个实施例包括在衬底的顶部区域的一部分中具有掩埋层的衬底，以便延伸漂移区域。在掩埋层和衬底之上形成层，并且彼此相邻地形成高压N阱和P阱区。场电介质位于高压N阱和P阱的部分上方，并且在高压P阱和高压N阱之间的沟道区上形成栅极电介质和栅极导体。晶体管的源极和漏极区位于高压P阱和高压N阱中。可选地，在场电介质下的N阱区域中形成P场环。在另一个实施例中，具有位于高压N阱中的分配区域的横向功率超结MOSFET被制造为具有延伸漂移区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式