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1. 发明申请

US20140315358A1 MANUFACTURING METHOD OF JUNCTION FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：连接场效应晶体管的制造方法
公开(公告)号：US20140315358A1
公开(公告)日：2014-10-23
申请号：US13866766
申请日：2013-04-19
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/66
CPC分类号： H01L29/66893 , H01L29/0649 , H01L29/0843 , H01L29/66901 , H01L29/808
摘要： The present invention discloses a manufacturing method of a junction field effect transistor (JFET). The manufacturing method includes: providing a substrate with a first conductive type, forming a channel region with a second conductive type, forming a field region with the first conductive type, forming a gate with the first conductive type, forming a source with the second conductive type, forming a drain with the second conductive type, and forming a lightly doped region with the second conductive type. The channel region is formed by an ion implantation process step, wherein the lightly doped region is formed by masking a predetermined region from accelerated ions of the ion implantation process step, and diffusing impurities with the second conductive type nearby the predetermined region into it with a thermal process step.
摘要翻译：本发明公开了一种结型场效应晶体管（JFET）的制造方法。该制造方法包括：提供具有第一导电类型的衬底，形成具有第二导电类型的沟道区，形成具有第一导电类型的场区，形成具有第一导电类型的栅极，形成具有第二导电形成具有第二导电类型的漏极，以及形成具有第二导电类型的轻掺杂区域。沟道区域通过离子注入工艺步骤形成，其中通过从离子注入工艺步骤的加速离子掩蔽预定区域并且将具有第二导电类型的杂质附近的预定区域的杂质扩散到其中以通过离子注入工艺步骤热处理步骤。

2. 发明授权

US08686504B2 Double diffused drain metal oxide semiconductor device and manufacturing method thereof 有权
公开(公告)号：US08686504B2
公开(公告)日：2014-04-01
申请号：US13555163
申请日：2012-07-22
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/66
CPC分类号： H01L29/78 , H01L21/823412 , H01L21/823418 , H01L27/088 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/66689 , H01L29/7816
摘要： The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.

3. 发明申请

US20150123198A1 HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：高压器件及其制造方法
公开(公告)号：US20150123198A1
公开(公告)日：2015-05-07
申请号：US14592306
申请日：2015-01-08
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L21/823418 , H01L29/0634 , H01L29/0692 , H01L29/0886 , H01L29/1045 , H01L29/41758 , H01L29/423 , H01L29/66659 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.
摘要翻译：本发明公开了一种高压器件及其制造方法。高电压装置包括：具有用于限定器件区域的隔离结构的衬底; 位于所述器件区域中的漂移区域，其中，从顶视图，所述漂移区域包括彼此分离但彼此电连接的多个子区域; 设备区域中的源极和漏极; 以及在衬底的表面上以及器件区域中的源极和漏极之间的栅极。

4. 发明申请

US20140151796A1 HYBRID HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：混合高压器件及其制造方法
公开(公告)号：US20140151796A1
公开(公告)日：2014-06-05
申请号：US14176973
申请日：2014-02-10
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/78
CPC分类号： H01L29/7817 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/402 , H01L29/42368 , H01L29/4238 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.
摘要翻译：本发明公开了一种混合式高压装置及其制造方法。混合高压器件形成在第一导电型衬底中，并且包括至少一个横向双扩散金属氧化物半导体（LDMOS）器件区域和至少一个通气器件区域，其中LDMOS器件区域和通气器件区域被连接在宽度方向上以交替的顺序布置。此外，LDMOS器件区域和通风装置区域的相应的高压井，源极，漏极，体区和栅极分别彼此连接。

5. 发明授权

US08575693B1 Double diffused metal oxide semiconductor device 有权
标题翻译：双扩散金属氧化物半导体器件
公开(公告)号：US08575693B1
公开(公告)日：2013-11-05
申请号：US13480360
申请日：2012-05-24
申请人： Tsung-Yi Huang , Chien-Wei Chiu , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Wei Chiu , Chien-Hao Huang
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/66681
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device. The DMOS device is formed in a substrate, and includes a high voltage well, a first field oxide region, a first gate, a first source, a drain, a body region, a body electrode, a second field oxide region, a second gate, and a second source. The second field oxide region and the first field oxide region are separated by the high voltage well and the body region. A part of the second gate is on the second field oxide region, and another part of the second gate is on the body region. The second gate is electrically connected to the first gate, and the second source is electrically connected to the first source, such that when the DMOS device is ON, a surface channel and a buried channel are formed.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）装置。 DMOS器件形成在衬底中，并且包括高电压阱，第一场氧化物区域，第一栅极，第一源极，漏极，体区域，体电极，第二场氧化物区域，第二栅极，和第二个来源。第二场氧化物区域和第一场氧化物区域被高电压井和身体区域分开。第二栅极的一部分在第二场氧化物区域上，第二栅极的另一部分位于主体区域上。第二栅极电连接到第一栅极，并且第二源极电连接到第一源极，使得当DMOS器件导通时，形成表面沟道和埋入沟道。

6. 发明授权

US08524586B2 Semiconductor overlapped PN structure and manufacturing method thereof 有权
标题翻译：半导体重叠PN结构及其制造方法
公开(公告)号：US08524586B2
公开(公告)日：2013-09-03
申请号：US13090449
申请日：2011-04-20
申请人： Tsung-Yi Huang , Chien-Hao Huang , Ying-Shiou Lin
发明人： Tsung-Yi Huang , Chien-Hao Huang , Ying-Shiou Lin
IPC分类号： H01L21/334
CPC分类号： H01L29/06 , H01L21/266 , H01L29/0688 , H01L29/36
摘要： The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.
摘要翻译：本发明公开了半导体重叠PN结构及其制造方法。该方法包括：提供衬底; 提供第一掩模以限定所述衬底中的P（或N）型阱和至少一个重叠区域; 将P（或N）型杂质注入P（或N）型阱和至少一个重叠区域; 提供具有至少一个开口的第二掩模，以在所述衬底中限定N（或P）型阱，并且在所述至少一个重叠区域中限定至少一个双注入区域; 将N（或P）型杂质注入N（或P）型阱和至少一个双注入区，使得至少一个双注入区具有P型和N型杂质。

7. 发明申请

US20130181253A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130181253A1
公开(公告)日：2013-07-18
申请号：US13353053
申请日：2012-01-18
申请人： Tsung-Yi Huang , Chien-Wei Chiu , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Wei Chiu , Chien-Hao Huang
IPC分类号： H01L29/72 , H01L21/331
CPC分类号： H01L29/7396 , H01L29/0611 , H01L29/0619 , H01L29/0623
摘要： The present invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure is formed in a first conductive type substrate, which has an upper surface. The semiconductor structure includes: a protected device, at least a buried trench, and at least a doped region. The protected device is formed in the substrate. The buried trench is formed below the upper surface with a first depth, and the buried trench surrounds the protected device from top view. The doped region is formed below the upper surface with a second depth, and the doped region surrounds the buried trench from top view. The second depth is not less than the first depth.
摘要翻译：本发明公开了一种半导体结构及其制造方法。半导体结构形成在具有上表面的第一导电型基板中。半导体结构包括：受保护器件，至少埋入沟槽和至少掺杂区域。受保护的器件形成在衬底中。埋设的沟槽形成在上表面下方具有第一深度，并且埋入的沟槽从顶视图围绕受保护的器件。掺杂区域形成在具有第二深度的上表面下方，并且掺杂区域从顶视图围绕埋入沟槽。第二深度不小于第一深度。

8. 发明申请

US20150028417A1 HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：高压器件及其制造方法
公开(公告)号：US20150028417A1
公开(公告)日：2015-01-29
申请号：US14483520
申请日：2014-09-11
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/78 , H01L29/06 , H01L29/10 , H01L29/08
CPC分类号： H01L29/0878 , H01L21/266 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/086 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.
摘要翻译：本发明公开了一种高压器件及其制造方法。高压器件形成在第一导电型衬底中，其中衬底包括限定器件区域的隔离区域。高电压装置包括：位于器件区域中的掺杂有第二导电类型杂质的漂移区; 在器件区域和衬底的表面上的栅极; 以及在栅极的不同侧的器件区域中的第二导电类型源极和漏极。从俯视图，漂移区域的第二导电型杂质的浓度沿水平方向和垂直方向大致周期性地分布。

9. 发明授权

US08685824B2 Hybrid high voltage device and manufacturing method thereof 有权
标题翻译：混合高压器件及其制造方法
公开(公告)号：US08685824B2
公开(公告)日：2014-04-01
申请号：US13529963
申请日：2012-06-21
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/7817 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/402 , H01L29/42368 , H01L29/4238 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.
摘要翻译：本发明公开了一种混合式高压装置及其制造方法。混合高压器件形成在第一导电型衬底中，并且包括至少一个横向双扩散金属氧化物半导体（LDMOS）器件区域和至少一个通气器件区域，其中LDMOS器件区域和通气器件区域被连接在宽度方向上以交替的顺序布置。此外，LDMOS器件区域和通风装置区域的相应的高压井，源极，漏极，体区和栅极分别彼此连接。

10. 发明申请

US20130256846A1 Semiconductor Overlapped PN Structure and Manufacturing Method Thereof 有权
标题翻译：半导体重叠PN结构及其制造方法
公开(公告)号：US20130256846A1
公开(公告)日：2013-10-03
申请号：US13864196
申请日：2013-04-16
申请人： Tsung-Yi Huang , Chien-Hao Huang , Ying-Shiou Lin
发明人： Tsung-Yi Huang , Chien-Hao Huang , Ying-Shiou Lin
IPC分类号： H01L29/06
CPC分类号： H01L29/06 , H01L21/266 , H01L29/0688 , H01L29/36
摘要： The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.
摘要翻译：本发明公开了半导体重叠PN结构及其制造方法。该方法包括：提供衬底; 提供第一掩模以限定所述衬底中的P（或N）型阱和至少一个重叠区域; 将P（或N）型杂质注入P（或N）型阱和至少一个重叠区域; 提供具有至少一个开口的第二掩模，以在所述衬底中限定N（或P）型阱，并且在所述至少一个重叠区域中限定至少一个双注入区域; 将N（或P）型杂质注入N（或P）型阱和至少一个双注入区，使得至少一个双注入区具有P型和N型杂质。

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