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141. 发明授权

US07343455B2 Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation 有权
标题翻译：缓存机制和方法，用于避免对不良受害者选择和回收受害者选择操作
公开(公告)号：US07343455B2
公开(公告)日：2008-03-11
申请号：US11054394
申请日：2005-02-09
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/123 , G06F2212/1032
摘要： A method, apparatus, and computer for identifying selection of a bad victim during victim selection at a cache and recovering from such bad victim selection without causing the system to crash or suspend forward progress of the victim selection process. Among the bad victim selection addressed are recovery from selection of a deleted member and recovery from use of LRU state bits that do not map to a member within the congruence class. When LRU victim selection logic generates an output vector identifying a victim, the output vector is checked to ensure that it is a valid vector (non-null) and that it is not pointing to a deleted member. When the output vector is not valid or points to a deleted member, the LRU victim selection logic is triggered to re-start the victim selection process.
摘要翻译：一种方法，装置和计算机，用于在高速缓存的受害者选择期间识别对不良受害者的选择，并从这种不良受害者选择中恢复，而不会导致系统崩溃或中止向前进行受害者选择过程。所解决的不良受害者选择之一是从选择已删除成员的恢复以及使用不映射到同余类中的成员的LRU状态位进行恢复。当LRU受害者选择逻辑生成识别受害者的输出向量时，检查输出向量以确保它是有效向量（非空值），并且不指向已删除的成员。当输出向量无效或指向被删除成员时，LRU受害者选择逻辑被触发以重新启动受害者选择过程。

142. 发明授权

US07305522B2 Victim cache using direct intervention 失效
标题翻译：受害者缓存使用直接干预
公开(公告)号：US07305522B2
公开(公告)日：2007-12-04
申请号：US11056649
申请日：2005-02-12
申请人： Leo James Clark , James Stephen Fields, Jr. , Guy Lynn Guthrie , Bradley David McCredie , William John Starke
发明人： Leo James Clark , James Stephen Fields, Jr. , Guy Lynn Guthrie , Bradley David McCredie , William John Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/127
摘要： A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.
摘要翻译：一种用于实现跨层级高速缓冲存储器的干预的方法，系统和设备。在优选实施例中，响应于第一高速缓冲存储器中的高速缓存未命中，直接干预请求从第一高速缓存存储器发送到第二高速缓存存储器，请求满足高速缓存未命中的直接干预。在替代实施例中，利用直接干预来访问相同级别的受害者缓存。

143. 发明授权

US07197604B2 Processor, data processing system and method for synchronzing access to data in shared memory 失效
标题翻译：处理器，数据处理系统和方法，用于同步共享存储器中数据的访问
公开(公告)号：US07197604B2
公开(公告)日：2007-03-27
申请号：US10965151
申请日：2004-10-14
申请人： Guy Lynn Guthrie , Sheldon B. Levenstein , William John Starke , Derek Edward Williams
发明人： Guy Lynn Guthrie , Sheldon B. Levenstein , William John Starke , Derek Edward Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0875 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3851
摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit. The instruction execution unit, responsive to receipt of a load-reserve instruction from the instruction sequencing unit, executes the load-reserve instruction to determine a load target address. The processor core, responsive to the execution of the load-reserve instruction, performs a corresponding load-reserve operation by accessing the store-through upper level cache utilizing the load target address to cause data associated with the load target address to be loaded from the store-through upper level cache into the data register and by establishing a reservation for a reservation granule including the load target address.
摘要翻译：一种用于多处理器数据处理系统的处理单元，包括：处理器核心，包括存储器上级缓存器，指令执行指令排序单元，数据寄存器和至少一个指令执行单元。指令执行单元响应于从指令排序单元接收到加载保留指令，执行加载保留指令以确定加载目标地址。处理器核心响应于负载预留指令的执行，通过使用负载目标地址访问存储上级高速缓存来执行相应的加载备份操作，以使与加载目标地址相关联的数据从通过上层缓存到数据寄存器中，并通过建立包括加载目标地址的预留颗粒的预留。

144. 发明授权

US10489293B2 Information handling system with immediate scheduling of load operations 有权
公开(公告)号：US10489293B2
公开(公告)日：2019-11-26
申请号：US12424284
申请日：2009-04-15
申请人： Sanjeev Ghai , Guy Lynn Guthrie , Stephen Powell , William John Starke
发明人： Sanjeev Ghai , Guy Lynn Guthrie , Stephen Powell , William John Starke
IPC分类号： G06F12/08 , G06F12/0855 , G06F12/126
CPC分类号： G06F12/0855 , G06F12/126
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.

145. 发明授权

US08230117B2 Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline 有权
标题翻译：在使用命令管道的一致性管理处理器系统中对写后排序进行排序的技术
公开(公告)号：US08230117B2
公开(公告)日：2012-07-24
申请号：US12420889
申请日：2009-04-09
申请人： George William Daly, Jr. , Guy Lynn Guthrie , Ross Boyd Leavens , Joseph Gerald McDonald , Michael Steven Siegel , William John Starke , Derek Edward Williams
发明人： George William Daly, Jr. , Guy Lynn Guthrie , Ross Boyd Leavens , Joseph Gerald McDonald , Michael Steven Siegel , William John Starke , Derek Edward Williams
IPC分类号： G06F3/00
CPC分类号： G06F13/4022
摘要： A technique for maintaining input/output (I/O) command ordering on a bus includes assigning a channel identifier to I/O commands of an I/O stream. In this case, the channel identifier indicates the I/O commands belong to the I/O stream. A command location indicator is assigned to each of the I/O commands. The command location indicator provides an indication of which one of the I/O commands is a start command in the I/O stream and which of the I/O commands are continue commands in the I/O stream. The I/O commands are issued in a desired completion order. When a first one of the I/O commands does not complete successfully, the I/O commands in the I/O stream are reissued on the bus starting at the first one of the I/O commands that did not complete successfully.
摘要翻译：用于在总线上维持输入/输出（I / O）命令排序的技术包括将信道标识符分配给I / O流的I / O命令。在这种情况下，通道标识符表示属于I / O流的I / O命令。命令位置指示符分配给每个I / O命令。命令位置指示器提供I / O命令中的哪一个是I / O流中的起始命令以及I / O命令中的哪一个在I / O流中继续命令的指示。 I / O命令以所需的完成顺序发出。当第一个I / O命令未成功完成时，I / O流中的I / O命令将从未成功完成的第一个I / O命令开始在总线上重新发出。

146. 发明授权

US08166246B2 Chaining multiple smaller store queue entries for more efficient store queue usage 有权
标题翻译：链接多个较小的存储队列条目，以实现更高效的存储队列使用
公开(公告)号：US08166246B2
公开(公告)日：2012-04-24
申请号：US12023600
申请日：2008-01-31
申请人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
发明人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0893 , G06F12/0815
摘要： A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry.
摘要翻译：数据处理系统中的计算机实现方法，处理器芯片，数据处理系统和计算机程序产品，处理数据处理系统的存储高速缓存中的信息。存储高速缓存接收包括指示高速缓存行的第一段的第一地址的第一条目。存储高速缓存然后接收包括指示高速缓存行的第二段的第二地址的第二条目。响应于第一段不等于第二段，第一个条目链接到第二个条目。

147. 发明授权

US08140756B2 Information handling system with immediate scheduling of load operations and fine-grained access to cache memory 有权
标题翻译：信息处理系统，可立即调度加载操作，并对缓存进行细粒度访问
公开(公告)号：US08140756B2
公开(公告)日：2012-03-20
申请号：US12424332
申请日：2009-04-15
申请人： Sanjeev Gai , Guy Lynn Guthrie , Stephen Powell , William John Starke
发明人： Sanjeev Gai , Guy Lynn Guthrie , Stephen Powell , William John Starke
IPC分类号： G06F13/00
CPC分类号： G06F12/0822
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption. The control logic determines the size requirement of each load operation or store operation. When the cache memory system performs a store operation or load operation, the memory system accesses the portion of a cache line it needs to perform the operation instead of accessing an entire cache line.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。当L2高速缓存存储器完成对中断加载请求的服务时，L2高速缓冲存储器可以在中断点返回服务中断的存储请求。控制逻辑确定每个加载操作或存储操作的大小要求。当高速缓冲存储器系统执行存储操作或加载操作时，存储器系统访问它需要执行操作的高速缓存行的部分，而不是访问整个高速缓存行。

148. 发明申请

US20100268887A1 INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH DUAL DISPATCH INTO WRITE/READ DATA FLOW 有权
标题翻译：信息处理系统具有立即调度双币种缓存中的负载操作，双重分配到写/读数据流
公开(公告)号：US20100268887A1
公开(公告)日：2010-10-21
申请号：US12424255
申请日：2009-04-15
申请人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides dual dispatch points into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。缓存系统向数据流提供双调度点到二级高速缓冲存储器的双缓存组。

149. 发明授权

US07783834B2 L2 cache array topology for large cache with different latency domains 有权
标题翻译：具有不同延迟域的大型缓存的L2缓存阵列拓扑
公开(公告)号：US07783834B2
公开(公告)日：2010-08-24
申请号：US11947742
申请日：2007-11-29
申请人： Leo James Clark , Guy Lynn Guthrie , Kirk Samuel Livingston , William John Starke
发明人： Leo James Clark , Guy Lynn Guthrie , Kirk Samuel Livingston , William John Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0822 , G06F12/0824
摘要： A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires having a higher transmission speed are preferably used to output the cache line corresponding to the requested memory block. In the illustrative embodiment the cache is arranged with rows and columns of the cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency. One set of wires oriented along a horizontal direction may be used to output the cache line, while another set of wires oriented along a vertical direction may be used for maintenance of the cache sectors. A given cache line is further preferably spread across sectors in different rows or cache ways. For example, a cache line can be 128 bytes and spread across four sectors in four different columns, each sector containing 32 bytes of the cache line, and the cache line is output over four successive clock cycles with one sector being transmitted during each of the four cycles.
摘要翻译：缓存存储器逻辑地将高速缓存行与高速缓存阵列的至少两个缓存扇区相关联，其中不同扇区具有不同的输出延迟，并且对于负载命中，基于它们的等待时间来选择性地启用高速缓存扇区以在连续的时钟周期上输出高速缓存行。优选使用具有较高传输速度的较大导线来输出与所请求的存储块相对应的高速缓存行。在说明性实施例中，高速缓存器配置有高速缓存扇区的行和列，并且给定的高速缓存行分布在不同列中的扇区之间，其中给定高速缓存行的至少一部分位于具有第一等待时间的第一列中并且所述给定高速缓存行的另一部分位于具有大于所述第一等待时间的第二等待时间的第二列中。可以使用沿水平方向定向的一组线来输出高速缓存线，而沿着垂直方向定向的另一组线可以用于高速缓存扇区的维护。给定的高速缓存行进一步优选地分布在不同行或高速缓存方式的扇区之间。例如，高速缓存行可以是128字节并且分布在四个不同列中的四个扇区上，每个扇区包含32个字节的高速缓存行，并且高速缓存行在四个连续的时钟周期内被输出，在每个四个周期。

150. 发明授权

US07774555B2 Data processing system and method for efficient coherency communication utilizing coherency domain indicators 有权
标题翻译：数据处理系统和方法，利用相干域指标进行有效的一致性通信
公开(公告)号：US07774555B2
公开(公告)日：2010-08-10
申请号：US11835259
申请日：2007-08-07
申请人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0826
摘要： In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.
摘要翻译：在包括至少第一和第二相干域的缓存相干数据处理系统中，存储器块与指示是否缓存存储器块的域指示符相关联地存储在系统存储器中，如果有的话，只有在第一一致性内域。第一相干域中的主设备通过参考存储在高速缓存中的域指示符来确定操作的广播传输的范围是否应超出第一相关域，然后在高速缓存相干数据处理中执行操作的广播系统按照确定。

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