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131. 发明授权

US07898306B1 High bandwidth phase locked loop (PLL) with feedback loop including a frequency divider 有权
标题翻译：具有反馈环路的高带宽锁相环（PLL）包括分频器
公开(公告)号：US07898306B1
公开(公告)日：2011-03-01
申请号：US12235507
申请日：2008-09-22
申请人： Chi Fung Cheng
发明人： Chi Fung Cheng
IPC分类号： H03L7/16
CPC分类号： H03L7/081
摘要： A phase locked loop (PLL) is provided. In one implementation, the PLL includes a multiphase voltage controlled oscillator (VCO) operable to generate an output signal containing one or more phase signals, a programmable divider operable to divide a frequency of the output signal of the multiphase VCO to produce a divided frequency output signal, and a fractional divider to fractionally divide an input phase signal. The fractional divider can include an integer divider operable to receive the input phase signal and divide the input phase signal in accordance with an integer divisor to produce a divided signal as an input to the multiphase VCO, and a phase interpolator operable to select a phase signal from among the one or more phase signals output by the multiphase VCO, to produce an interpolated output signal having a desired frequency resolution.
摘要翻译：提供锁相环（PLL）。在一个实现中，PLL包括可操作以产生包含一个或多个相位信号的输出信号的多相压控振荡器（VCO），可编程分频器，可操作以分频多相VCO的输出信号的频率以产生分频输出信号和一个分数分频器来对输入相位信号进行分数分频。分数除法器可以包括一个整数除法器，可操作用于接收输入相位信号，并根据整数除数分频输入相位信号，以产生分频信号作为多相VCO的输入;以及相位插值器，可操作以选择相位信号从由多相VCO输出的一个或多个相位信号中产生具有期望频率分辨率的内插输出信号。

132. 发明授权

US07750742B2 Enhanced all digital phase-locked loop and oscillation signal generation method thereof 失效
标题翻译：增强了所有数字锁相环及其振荡信号的产生方法
公开(公告)号：US07750742B2
公开(公告)日：2010-07-06
申请号：US12264811
申请日：2008-11-04
申请人： Seonghwan Cho , Wookon Son
发明人： Seonghwan Cho , Wookon Son
IPC分类号： H03L7/06 , H03L7/16
CPC分类号： H03L7/087 , H03L7/093 , H03L2207/50
摘要： An All Digital PLL (ADPLL) and oscillation signal generation method using the ADPLL is provided for generating a spur-free oscillation signal by improving the frequency resolution of the ADPLL. An all digital phase-locked loop of the present invention includes a digitally controlled oscillator for generating an oscillation signal having a frequency corresponding to an inputted control signal, a re-timer for retiming a reference clock based on the oscillation signal, a feedback circuit for accumulating a number of clocks of the oscillation signal within a time period and generating a phase information of the oscillation signal in synchronization with the retimed reference clock, a sigma-delta modulator for sigma-delta modulating a frequency command signal into a modulation signal having a less number of bits than a number of bits of the frequency command signal, a reference phase accumulator for accumulating phases corresponding to the modulation signal, a phase difference detector for generating a phase difference information between an output signal of the reference phase accumulator and the phase information, and a digital loop filter for filtering the phase difference information to generate the control signal.
摘要翻译：提供使用ADPLL的全数字PLL（ADPLL）和振荡信号产生方法，通过提高ADPLL的频率分辨率来产生无杂散振荡信号。本发明的全数字锁相环包括用于产生具有与输入的控制信号对应的频率的振荡信号的数字控制振荡器，用于基于振荡信号对基准时钟重新定时的重定时器，用于在一个时间周期内累积振荡信号的多个时钟，并且与重新定时的参考时钟同步地产生振荡信号的相位信息;Σ-Δ调制器，用于将频率指令信号的Σ-Δ调制成具有比频率指令信号的位数少的位数，用于累加对应于调制信号的相位的基准相位累加器，用于产生参考相位累加器的输出信号与相位相位之间的相位差信息的相位差检测器信息和用于过滤相位差信息的数字环路滤波器生成控制信号。

133. 发明授权

US07737791B2 Spread spectrum clocking in fractional-N PLL 有权
$Spread spectrum clocking in fractional-N PLL$
标题翻译：在分数N PLL中扩展频谱时钟
公开(公告)号：US07737791B2
公开(公告)日：2010-06-15
申请号：US12205586
申请日：2008-09-05
申请人： Puneet Sareen , Hermann Seibold
发明人： Puneet Sareen , Hermann Seibold
IPC分类号： H03L7/08 , H03L7/16
CPC分类号： H03L7/0998 , H03L7/0996 , H03L7/18
摘要： In applications that use fractional-N phase locked loops (PLLs), the use of spread spectrum clocking (SSC) to reduced electromagnetic interference (EMI) would be desirable, but conflicts can occur. Here, a circuit is provided that includes both fractional logic circuitry and spread spectrum logic circuitry. This logic circuitry operates in combination with a phase selector to generally ensure that the likelihood of conflicts (which can occur in conventional circuit) are reduced.
摘要翻译：在使用分数N锁相环（PLL）的应用中，需要使用扩频时钟（SSC）来降低电磁干扰（EMI），但可能发生冲突。这里提供了包括分数逻辑电路和扩频逻辑电路的电路。该逻辑电路与相位选择器组合工作，以通常确保减少冲突的可能性（可能在常规电路中发生）。

134. 发明授权

US07548123B2 Dividerless PLL architecture 有权
标题翻译：无分频PLL架构
公开(公告)号：US07548123B2
公开(公告)日：2009-06-16
申请号：US11777779
申请日：2007-07-13
申请人： Douglas R. Frey
发明人： Douglas R. Frey
IPC分类号： H03L7/16 , H03L7/18
CPC分类号： H03L7/0802 , H03L7/085 , H03L7/087 , H03L7/0891 , H03L7/10 , H03L7/1976
摘要： A phase-locked loop (PLL) achieves initial lock using a course fractional-N divider driving a binary phase detector. Once frequency lock is achieved, this divider may be turned off, while an adaptive phase detector takes over control of the PLL front end. The adaptive phase detector (APD) receives input directly from the VCO and the reference clock, deriving digital control signals and a precision phase detector output. The APD operates at the update rate, generating a digital delta sigma modulator (DSM) data stream output at the update rate. The APD automatically locks to a digitally generated ramp corresponding to an expected difference between the VCO output and the reference clock, while adaptively correcting for DC errors and ramp cancellation errors.
摘要翻译：锁相环（PLL）使用驱动二进制相位检测器的路线分数N分频器来实现初始锁定。一旦达到频率锁定，该分频器可能会关闭，而自适应相位检测器接管PLL前端的控制。自适应相位检测器（APD）直接从VCO和参考时钟接收输入，导出数字控制信号和精密相位检测器输出。 APD以更新速率工作，产生以更新速率输出的数字Δ-Σ调制器（DSM）数据流。 APD自动锁定到与VCO输出和参考时钟之间的期望差异相对应的数字产生的斜坡，同时自适应地校正DC误差和斜坡消除误差。

135. 发明申请

US20090085673A1 METHOD AND SYSTEM FOR SIGNAL GENERATION VIA A PLL WITH DDFS FEEDBACK PATH 失效
标题翻译：用于通过DDFS反馈路径进行信号生成的方法和系统
公开(公告)号：US20090085673A1
公开(公告)日：2009-04-02
申请号：US11863531
申请日：2007-09-28
申请人： Ahmadreza Rofougaran
发明人： Ahmadreza Rofougaran
IPC分类号： H03L7/18 , H03L7/16
CPC分类号： H03L7/1806 , H03L7/0891
摘要： Aspects of a method and system for signal generation via a PLL with a DDFS feedback path are provided. In this regard, a phase difference between a reference signal and a feedback signal may be utilized to control a VCO, wherein the feedback signal is generated by a DDFS. Voltage, current and/or power levels of the generated feedback signal may be limited to a determined range of values. Moreover, the feedback signal may be based on an output of the VCO and a digital control word input to the DDFS. The digital control word may be programmatically controlled by, for example, a processor. Additionally, the control word may be determined based on a desired frequency of the generated feedback signal and a desired output frequency of the VCO. Accordingly, the DDFS may be clocked by the output of the VCO, or by a divided down version of the VCO output.
摘要翻译：提供了通过具有DDFS反馈路径的PLL产生信号的方法和系统的方面。在这方面，可以利用参考信号和反馈信号之间的相位差来控制VCO，其中反馈信号由DDFS产生。产生的反馈信号的电压，电流和/或功率电平可以被限制在确定的值范围内。此外，反馈信号可以基于VCO的输出和输入到DDFS的数字控制字。数字控制字可以由例如处理器编程控制。另外，可以基于产生的反馈信号的期望频率和VCO的期望输出频率来确定控制字。因此，DDFS可以由VCO的输出或VCO输出的分频版本来计时。

136. 发明申请

US20090066423A1 SPREAD SPECTRUM CLOCKING IN FRACTIONAL-N PLL 有权
标题翻译：分频N PLL中的频谱分频
公开(公告)号：US20090066423A1
公开(公告)日：2009-03-12
申请号：US12205586
申请日：2008-09-05
申请人： Puneet Sareen , Hermann Seibold
发明人： Puneet Sareen , Hermann Seibold
IPC分类号： H03L7/16
CPC分类号： H03L7/0998 , H03L7/0996 , H03L7/18
摘要： A combined spread spectrum and fractional-N phase locked loop circuit comprises a chain of a reference clock divider, a phase-frequency detector, a charge pump with loop filter, a voltage controlled oscillator that provides multiple phase outputs, and a feedback loop from the multiple phase outputs of the voltage controlled oscillator to a feedback input of the phase-frequency detector. The feedback loop includes a phase selector, a feedback divider and a control block with an output controlling said phase selector to select a particular phase as an input to the feedback divider. The control block includes spread spectrum logic circuitry receiving an input from the output of the phase selector and providing a directional control output signal and a phase step control signal. The control block further includes fractional logic circuitry receiving an input from the output of the phase selector and providing a phase step control signal. A logic interface circuit combines the directional control output signal from the spread spectrum logic circuitry, the phase step control signal from the spread spectrum logic circuitry, and the phase step control signal from the fractional logic circuitry. This means that when both of the spread spectrum logic circuitry and the fractional logic circuitry request a phase step in the same feedback clock period in the same direction, a single phase step control signal is passed to the phase selector and a further phase step control signal is passed to the phase selector in a subsequent clock period. Further, when the spread spectrum logic circuitry and the fractional logic circuitry request a phase step in the same feedback clock period in opposite directions, no phase step control signal is passed to the phase selector.
摘要翻译：组合扩频和分数N锁相环电路包括一个参考时钟分频器链，一个相位频率检测器，一个带环路滤波器的电荷泵，一个提供多相输出的压控振荡器，以及一个来自压控振荡器的多相输出到相位检波器的反馈输入。反馈回路包括相位选择器，反馈分频器和具有输出的控制块，控制所述相位选择器以选择特定相位作为反馈分频器的输入。控制块包括扩频逻辑电路，其接收来自相位选择器的输出的输入，并提供方向控制输出信号和相位步进控制信号。控制块还包括分数逻辑电路，其从相位选择器的输出接收输入并提供相位步进控制信号。逻辑接口电路组合来自扩频逻辑电路的方向控制输出信号，来自扩展频谱逻辑电路的相位步进控制信号和来自分数逻辑电路的相位步进控制信号。这意味着当扩展频谱逻辑电路和分数逻辑电路两者在相同方向上在相同的反馈时钟周期中请求相位阶跃时，单相步进控制信号被传递到相位选择器和另一相位步进控制信号在随后的时钟周期内被传递到相位选择器。此外，当扩展频谱逻辑电路和分数逻辑电路在相反的方向上在相同的反馈时钟周期内请求相位阶跃时，没有相位步进控制信号被传递到相位选择器。

137. 发明授权

US07406297B2 Clock generation circuit and semiconductor device provided therewith 有权
公开(公告)号：US07406297B2
公开(公告)日：2008-07-29
申请号：US11417181
申请日：2006-05-04
申请人： Takeshi Osada
发明人： Takeshi Osada
IPC分类号： H03B5/00 , H03L7/06 , H03L7/16 , H04B1/40
CPC分类号： H03L7/0995 , H03L7/18
摘要： It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal.

138. 发明授权

US07216249B2 Clock generation system 有权
标题翻译：时钟发生系统
公开(公告)号：US07216249B2
公开(公告)日：2007-05-08
申请号：US10457149
申请日：2003-06-09
申请人： Masayu Fujiwara , Masaki Onishi
发明人： Masayu Fujiwara , Masaki Onishi
IPC分类号： G06F1/04 , G06F1/06 , G06F1/10 , H03L7/16 , H03L7/18 , H03B19/12 , H03K3/03 , H03K21/00 , H03K23/00
CPC分类号： H03L7/23 , G06F1/06 , G11B20/1403
摘要： A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a reference clock, using PL circuits in such a way that the clocks have sufficient S/N ratios in spite of the S/N ratio limitation by the noise floor. A first reference frequency clock is supplied to a first PLL circuit to generate an intermediate-frequency clock having an intermediate frequency having a predetermined ratio to the reference clock. The intermediate-frequency clock is supplied to a second and a third PLL circuits to generate a second and a third reference frequency clocks having frequencies respectively having a second and a third ratios to the intermediate frequency, respectively.
摘要翻译：一种时钟发生系统，用于使用PL电路产生具有与参考时钟的参考频率具有预定比率的各个频率的第一，第二和第三参考频率时钟，使得时钟具有足够的S / 尽管S / N比受到本底噪声的限制，N比也是如此。第一参考频率时钟被提供给第一PLL电路以产生具有与参考时钟具有预定比率的中频的中频时钟。中频时钟被提供给第二和第三PLL电路，以分别产生具有分别具有与中频的第二和第三比率的频率的第二和第三参考频率时钟。

139. 发明申请

US20050277397A1 Frequency generator 审中-公开
标题翻译：频率发生器
公开(公告)号：US20050277397A1
公开(公告)日：2005-12-15
申请号：US11140259
申请日：2005-05-27
申请人： Niels Christoffers , Bedrich Hosticka , Rainer Kokozinski , Peter Jung
发明人： Niels Christoffers , Bedrich Hosticka , Rainer Kokozinski , Peter Jung
IPC分类号： H03L7/091 , H03L7/12 , H03L7/16 , H03L7/20 , H04B1/06 , H04B1/40 , H04B7/00
CPC分类号： H03L7/091 , H03L7/12 , H03L7/16 , H03L7/20
摘要： A frequency generator according to the invention includes a controllable oscillator comprising a control input and an oscillator output, wherein the controllable oscillator is formed to output, at the oscillator output, an oscillator signal with an oscillator frequency dependent on a control signal at the control input, sampling means for sampling the oscillator signal or a signal of the controllable oscillator derived therefrom with a reference frequency, in order to obtain a sample signal, and a low-pass filter for low-pass filtering the sample signal or a signal derived therefrom, in order to obtain the control signal or a signal underlying the control signal. Due to the less intensive construction, in particular the lack of a frequency divider, and the quicker adjustability of the currently generated frequency, according to the invention, more current-saving frequency generation may be obtained.
摘要翻译：根据本发明的频率发生器包括可控振荡器，其包括控制输入和振荡器输出，其中可控振荡器被形成为在振荡器输出处输出具有取决于控制输入端的控制信号的振荡器频率的振荡器信号采样装置，用于采样参考频率的振荡器信号或由其产生的可控振荡器的信号，以获得采样信号;以及低通滤波器，用于对采样信号或从其导出的信号进行低通滤波，以获得控制信号或控制信号的信号。由于根据本发明的结构较少，特别是缺少分频器，并且根据本发明可以更快地调整可调节性，因此可以获得更节省频率的产生。

140. 发明申请

US20050248373A1 Frequency synthesizer with digital phase selection 失效
标题翻译：具有数字相位选择的频率合成器
公开(公告)号：US20050248373A1
公开(公告)日：2005-11-10
申请号：US10838395
申请日：2004-05-04
申请人： Samuel Naffziger , Shahram Ghahremani
发明人： Samuel Naffziger , Shahram Ghahremani
IPC分类号： G06F1/12 , G06F1/08 , H02M3/315 , H03L7/08 , H03L7/081 , H03L7/16
CPC分类号： H03L7/16 , H03L7/081 , H03L7/0812
摘要： Systems, methodologies, media, and other embodiments associated with making a frequency change through frequency synthesis and digital selection of out-of-phase synthesized signals are described. One exemplary system embodiment includes a locked loop logic (e.g., phase locked, delay locked) that may receive a reference clock signal, process the reference clock signal into signals with different phases, and make those signals available to a selection logic. The exemplary system may also include a state logic that stores frequency divisors that facilitate selecting and tracking output signals provided by the selection logic. The exemplary system may also include a phase logic that stores output signal phase data associated with computing, describing, and/or selecting an output signal.
摘要翻译：描述了通过频率合成和异相合成信号的数字选择进行频率改变的系统，方法，媒体和其它实施例。一个示例性系统实施例包括可以接收参考时钟信号的锁定环路逻辑（例如，锁相，延迟锁定），将参考时钟信号处理成具有不同相位的信号，并使这些信号可用于选择逻辑。示例性系统还可以包括状态逻辑，其存储有助于选择和跟踪由选择逻辑提供的输出信号的频率因数。示例性系统还可以包括相位逻辑，其存储与计算，描述和/或选择输出信号相关联的输出信号相位数据。

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